hc32f448_driver_sys 0.1.0

Provide driver function binding for HDSC's HC32F448 MCU.
Documentation 
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/* automatically generated by rust-bindgen 0.72.1 */

pub const SPI_4_WIRE: u32 = 0;
pub const SPI_3_WIRE: u32 = 1;
pub const SPI_FULL_DUPLEX: u32 = 0;
pub const SPI_SEND_ONLY: u32 = 2;
pub const SPI_SLAVE: u32 = 0;
pub const SPI_MASTER: u32 = 8;
pub const SPI_LOOPBACK_INVD: u32 = 0;
pub const SPI_LOOPBACK_MOSI_INVT: u32 = 16;
pub const SPI_LOOPBACK_MOSI: u32 = 32;
pub const SPI_INT_ERR: u32 = 256;
pub const SPI_INT_TX_BUF_EMPTY: u32 = 512;
pub const SPI_INT_RX_BUF_FULL: u32 = 1024;
pub const SPI_INT_IDLE: u32 = 2048;
pub const SPI_INT_ALL: u32 = 3840;
pub const SPI_MD_FAULT_DETECT_DISABLE: u32 = 0;
pub const SPI_MD_FAULT_DETECT_ENABLE: u32 = 4096;
pub const SPI_PARITY_INVD: u32 = 0;
pub const SPI_PARITY_EVEN: u32 = 32768;
pub const SPI_PARITY_ODD: u32 = 49152;
pub const SPI_PIN_SS0: u32 = 256;
pub const SPI_PIN_SS1: u32 = 512;
pub const SPI_PIN_SS2: u32 = 1024;
pub const SPI_PIN_SS3: u32 = 2048;
pub const SPI_SS_VALID_LVL_HIGH: u32 = 1;
pub const SPI_SS_VALID_LVL_LOW: u32 = 0;
pub const SPI_RD_TARGET_RD_BUF: u32 = 0;
pub const SPI_RD_TARGET_WR_BUF: u32 = 64;
pub const SPI_1_FRAME: u32 = 0;
pub const SPI_2_FRAME: u32 = 1;
pub const SPI_3_FRAME: u32 = 2;
pub const SPI_4_FRAME: u32 = 3;
pub const SPI_INTERVAL_TIME_1SCK: u32 = 0;
pub const SPI_INTERVAL_TIME_2SCK: u32 = 268435456;
pub const SPI_INTERVAL_TIME_3SCK: u32 = 536870912;
pub const SPI_INTERVAL_TIME_4SCK: u32 = 805306368;
pub const SPI_INTERVAL_TIME_5SCK: u32 = 1073741824;
pub const SPI_INTERVAL_TIME_6SCK: u32 = 1342177280;
pub const SPI_INTERVAL_TIME_7SCK: u32 = 1610612736;
pub const SPI_INTERVAL_TIME_8SCK: u32 = 1879048192;
pub const SPI_RELEASE_TIME_1SCK: u32 = 0;
pub const SPI_RELEASE_TIME_2SCK: u32 = 16777216;
pub const SPI_RELEASE_TIME_3SCK: u32 = 33554432;
pub const SPI_RELEASE_TIME_4SCK: u32 = 50331648;
pub const SPI_RELEASE_TIME_5SCK: u32 = 67108864;
pub const SPI_RELEASE_TIME_6SCK: u32 = 83886080;
pub const SPI_RELEASE_TIME_7SCK: u32 = 100663296;
pub const SPI_RELEASE_TIME_8SCK: u32 = 117440512;
pub const SPI_SETUP_TIME_1SCK: u32 = 0;
pub const SPI_SETUP_TIME_2SCK: u32 = 1048576;
pub const SPI_SETUP_TIME_3SCK: u32 = 2097152;
pub const SPI_SETUP_TIME_4SCK: u32 = 3145728;
pub const SPI_SETUP_TIME_5SCK: u32 = 4194304;
pub const SPI_SETUP_TIME_6SCK: u32 = 5242880;
pub const SPI_SETUP_TIME_7SCK: u32 = 6291456;
pub const SPI_SETUP_TIME_8SCK: u32 = 7340032;
pub const SPI_COM_SUSP_FUNC_OFF: u32 = 0;
pub const SPI_COM_SUSP_FUNC_ON: u32 = 128;
pub const SPI_MD_0: u32 = 0;
pub const SPI_MD_1: u32 = 1;
pub const SPI_MD_2: u32 = 2;
pub const SPI_MD_3: u32 = 3;
pub const SPI_SCK_POLARITY_LOW: u32 = 0;
pub const SPI_SCK_POLARITY_HIGH: u32 = 2;
pub const SPI_SCK_PHASE_ODD_EDGE_SAMPLE: u32 = 0;
pub const SPI_SCK_PHASE_EVEN_EDGE_SAMPLE: u32 = 1;
pub const SPI_BR_CLK_DIV2: u32 = 0;
pub const SPI_BR_CLK_DIV4: u32 = 4096;
pub const SPI_BR_CLK_DIV6: u32 = 8192;
pub const SPI_BR_CLK_DIV8: u32 = 12288;
pub const SPI_BR_CLK_DIV10: u32 = 16384;
pub const SPI_BR_CLK_DIV12: u32 = 20480;
pub const SPI_BR_CLK_DIV14: u32 = 24576;
pub const SPI_BR_CLK_DIV16: u32 = 28672;
pub const SPI_BR_CLK_DIV18: u32 = 32768;
pub const SPI_BR_CLK_DIV20: u32 = 36864;
pub const SPI_BR_CLK_DIV22: u32 = 40960;
pub const SPI_BR_CLK_DIV24: u32 = 45056;
pub const SPI_BR_CLK_DIV26: u32 = 49152;
pub const SPI_BR_CLK_DIV28: u32 = 53248;
pub const SPI_BR_CLK_DIV30: u32 = 57344;
pub const SPI_BR_CLK_DIV32: u32 = 61440;
pub const SPI_BR_CLK_DIV36: u32 = 32772;
pub const SPI_BR_CLK_DIV40: u32 = 36868;
pub const SPI_BR_CLK_DIV44: u32 = 40964;
pub const SPI_BR_CLK_DIV48: u32 = 45060;
pub const SPI_BR_CLK_DIV52: u32 = 49156;
pub const SPI_BR_CLK_DIV56: u32 = 53252;
pub const SPI_BR_CLK_DIV60: u32 = 57348;
pub const SPI_BR_CLK_DIV64: u32 = 61444;
pub const SPI_BR_CLK_DIV72: u32 = 32776;
pub const SPI_BR_CLK_DIV80: u32 = 36872;
pub const SPI_BR_CLK_DIV88: u32 = 40968;
pub const SPI_BR_CLK_DIV96: u32 = 45064;
pub const SPI_BR_CLK_DIV104: u32 = 49160;
pub const SPI_BR_CLK_DIV112: u32 = 53256;
pub const SPI_BR_CLK_DIV120: u32 = 57352;
pub const SPI_BR_CLK_DIV128: u32 = 61448;
pub const SPI_BR_CLK_DIV144: u32 = 32780;
pub const SPI_BR_CLK_DIV160: u32 = 36876;
pub const SPI_BR_CLK_DIV176: u32 = 40972;
pub const SPI_BR_CLK_DIV192: u32 = 45068;
pub const SPI_BR_CLK_DIV208: u32 = 49164;
pub const SPI_BR_CLK_DIV224: u32 = 53260;
pub const SPI_BR_CLK_DIV240: u32 = 57356;
pub const SPI_BR_CLK_DIV256: u32 = 61452;
pub const SPI_DATA_SIZE_4BIT: u32 = 0;
pub const SPI_DATA_SIZE_5BIT: u32 = 256;
pub const SPI_DATA_SIZE_6BIT: u32 = 512;
pub const SPI_DATA_SIZE_7BIT: u32 = 768;
pub const SPI_DATA_SIZE_8BIT: u32 = 1024;
pub const SPI_DATA_SIZE_9BIT: u32 = 1280;
pub const SPI_DATA_SIZE_10BIT: u32 = 1536;
pub const SPI_DATA_SIZE_11BIT: u32 = 1792;
pub const SPI_DATA_SIZE_12BIT: u32 = 2048;
pub const SPI_DATA_SIZE_13BIT: u32 = 2304;
pub const SPI_DATA_SIZE_14BIT: u32 = 2560;
pub const SPI_DATA_SIZE_15BIT: u32 = 2816;
pub const SPI_DATA_SIZE_16BIT: u32 = 3072;
pub const SPI_DATA_SIZE_20BIT: u32 = 3328;
pub const SPI_DATA_SIZE_24BIT: u32 = 3584;
pub const SPI_DATA_SIZE_32BIT: u32 = 3840;
pub const SPI_FIRST_MSB: u32 = 0;
pub const SPI_FIRST_LSB: u32 = 4096;
pub const SPI_COMM_MD_NORMAL: u32 = 0;
pub const SPI_COMM_MD_CONT: u32 = 4;
pub const SPI_FLAG_OVERRUN: u32 = 1;
pub const SPI_FLAG_IDLE: u32 = 2;
pub const SPI_FLAG_MD_FAULT: u32 = 4;
pub const SPI_FLAG_PARITY_ERR: u32 = 8;
pub const SPI_FLAG_UNDERRUN: u32 = 16;
pub const SPI_FLAG_TX_BUF_EMPTY: u32 = 32;
pub const SPI_FLAG_RX_BUF_FULL: u32 = 128;
pub const SPI_FLAG_CLR_ALL: u32 = 29;
pub const SPI_FLAG_ALL: u32 = 191;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief SPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SPI_TypeDef {
    pub DR: u32,
    pub CR: u32,
    pub RESERVED0: [u8; 4usize],
    pub CFG1: u32,
    pub RESERVED1: [u8; 4usize],
    pub SR: u32,
    pub CFG2: u32,
}
#[doc = " @brief Structure definition of SPI initialization.\n @note The parameter u32BaudRatePrescaler is invalid while slave mode"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_init_t {
    #[doc = "< SPI wire mode, 3 wire mode or 4 wire mode.\nThis parameter can be a value of @ref SPI_Wire_Mode_Define"]
    pub u32WireMode: u32,
    #[doc = "< SPI transfer mode, send only or full duplex.\nThis parameter can be a value of @ref SPI_Trans_Mode_Define"]
    pub u32TransMode: u32,
    #[doc = "< SPI master/slave mode.\nThis parameter can be a value of @ref SPI_Master_Slave_Mode_Define"]
    pub u32MasterSlave: u32,
    #[doc = "< SPI mode fault detect command.\nThis parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define"]
    pub u32ModeFaultDetect: u32,
    #[doc = "< SPI parity check selection.\nThis parameter can be a value of @ref SPI_Parity_Check_Define"]
    pub u32Parity: u32,
    #[doc = "< SPI mode.\nThis parameter can be a value of @ref SPI_Mode_Define"]
    pub u32SpiMode: u32,
    #[doc = "< SPI baud rate prescaler.\nThis parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define"]
    pub u32BaudRatePrescaler: u32,
    #[doc = "< SPI data bits, 4 bits ~ 32 bits.\nThis parameter can be a value of @ref SPI_Data_Size_Define"]
    pub u32DataBits: u32,
    #[doc = "< MSB first or LSB first.\nThis parameter can be a value of @ref SPI_First_Bit_Define"]
    pub u32FirstBit: u32,
    #[doc = "< SPI communication suspend function.\nThis parameter can be a value of @ref SPI_Com_Suspend_Func_Define"]
    pub u32SuspendMode: u32,
    #[doc = "< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME.\nThis parameter can be a value of @ref SPI_Frame_Level_Define"]
    pub u32FrameLevel: u32,
}
#[doc = " @brief Structure definition of SPI delay time configuration."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_delay_t {
    #[doc = "< SPI interval time delay (Next access delay time)\nThis parameter can be a value of @ref SPI_Interval_Delay_Time_define"]
    pub u32IntervalDelay: u32,
    #[doc = "< SPI release time delay (SCK invalid delay time)\nThis parameter can be a value of @ref SPI_Release_Delay_Time_define"]
    pub u32ReleaseDelay: u32,
    #[doc = "< SPI Setup time delay (SCK valid delay time) define\nThis parameter can be a value of @ref SPI_Setup_Delay_Time_define"]
    pub u32SetupDelay: u32,
}
unsafe extern "C" {
    #[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup SPI_Global_Functions\n @{"]
    pub fn SPI_StructInit(pstcSpiInit: *mut stc_spi_init_t) -> i32;
    pub fn SPI_Init(SPIx: *mut CM_SPI_TypeDef, pstcSpiInit: *const stc_spi_init_t) -> i32;
    pub fn SPI_DeInit(SPIx: *mut CM_SPI_TypeDef) -> i32;
    pub fn SPI_IntCmd(
        SPIx: *mut CM_SPI_TypeDef,
        u32IntType: u32,
        enNewState: en_functional_state_t,
    );
    pub fn SPI_Cmd(SPIx: *mut CM_SPI_TypeDef, enNewState: en_functional_state_t);
    pub fn SPI_WriteData(SPIx: *mut CM_SPI_TypeDef, u32Data: u32);
    pub fn SPI_ReadData(SPIx: *const CM_SPI_TypeDef) -> u32;
    pub fn SPI_GetStatus(SPIx: *const CM_SPI_TypeDef, u32Flag: u32) -> en_flag_status_t;
    pub fn SPI_ClearStatus(SPIx: *mut CM_SPI_TypeDef, u32Flag: u32);
    pub fn SPI_SetLoopbackMode(SPIx: *mut CM_SPI_TypeDef, u32Mode: u32);
    pub fn SPI_ParityCheckCmd(SPIx: *mut CM_SPI_TypeDef, enNewState: en_functional_state_t);
    pub fn SPI_SetSSValidLevel(SPIx: *mut CM_SPI_TypeDef, u32SSPin: u32, u32SSLevel: u32);
    pub fn SPI_SetSckPolarity(SPIx: *mut CM_SPI_TypeDef, u32Polarity: u32);
    pub fn SPI_SetSckPhase(SPIx: *mut CM_SPI_TypeDef, u32Phase: u32);
    pub fn SPI_DelayTimeConfig(
        SPIx: *mut CM_SPI_TypeDef,
        pstcDelayConfig: *const stc_spi_delay_t,
    ) -> i32;
    pub fn SPI_SSPinSelect(SPIx: *mut CM_SPI_TypeDef, u32SSPin: u32);
    pub fn SPI_SetReadBuf(SPIx: *mut CM_SPI_TypeDef, u32ReadBuf: u32);
    pub fn SPI_DelayStructInit(pstcDelayConfig: *mut stc_spi_delay_t) -> i32;
    pub fn SPI_SetCommMode(SPIx: *mut CM_SPI_TypeDef, u32Mode: u32);
    pub fn SPI_Trans(
        SPIx: *mut CM_SPI_TypeDef,
        pvTxBuf: *const ::core::ffi::c_void,
        u32TxLen: u32,
        u32Timeout: u32,
    ) -> i32;
    pub fn SPI_Receive(
        SPIx: *mut CM_SPI_TypeDef,
        pvRxBuf: *mut ::core::ffi::c_void,
        u32RxLen: u32,
        u32Timeout: u32,
    ) -> i32;
    pub fn SPI_TransReceive(
        SPIx: *mut CM_SPI_TypeDef,
        pvTxBuf: *const ::core::ffi::c_void,
        pvRxBuf: *mut ::core::ffi::c_void,
        u32Len: u32,
        u32Timeout: u32,
    ) -> i32;
}