gateconvert 0.1.1

The library to convert Gate circuit from/to foreign logic format.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

[dependencies.cnfgen]
version = "0.6.0"

[dependencies.flussab]
version = "0.3.1"

[dependencies.flussab-aiger]
version = "0.1"

[dependencies.flussab-cnf]
version = "0.3"

[dependencies.gategen]
version = "0.2.0"

[dependencies.gateutil]
version = "0.1.0"

[dependencies.static_init]
version = "1.0"

[dependencies.thiserror]
version = "1.0"

[lib]
name = "gateconvert"
path = "src/lib.rs"

[package]
authors = ["Mateusz Szpakowski"]
autobenches = false
autobins = false
autoexamples = false
autolib = false
autotests = false
build = false
categories = ["science", "mathematics"]
description = "The library to convert Gate circuit from/to foreign logic format."
documentation = "https://docs.rs/gateconvert"
edition = "2021"
keywords = ["gate", "logic", "circuit"]
license = "Apache-2.0"
name = "gateconvert"
readme = "README.md"
repository = "https://github.com/matszpk/gateconvert"
version = "0.1.1"

[package.metadata.docs.rs]
all-features = true
rustdoc-args = ["--cfg", "docsrs"]

[[test]]
name = "aiger"
path = "tests/aiger.rs"

[[test]]
name = "blif"
path = "tests/blif.rs"

[[test]]
name = "btor2"
path = "tests/btor2.rs"

[[test]]
name = "cnf"
path = "tests/cnf.rs"

[[test]]
name = "lib"
path = "tests/lib.rs"

[[test]]
name = "verilog"
path = "tests/verilog.rs"

[[test]]
name = "vhdl"
path = "tests/vhdl.rs"