fayalite 0.2.0

Hardware Description Language embedded in Rust, using FIRRTL's semantics
Documentation 
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
//! ### Wires
//!
//! Wires are kinda like variables, but unlike registers,
//! they have no memory (they're combinatorial).
//! You must [connect] to all wires, so they have a defined value.
//!
//! Wires create a Rust variable with type [`Expr<T>`] where `T` is the type of the wire.
//!
//! Wires follow [connection semantics], which are unlike assignments in software, so you should read it.
//!
//! ```
//! # use fayalite::prelude::*;
//! # #[hdl_module]
//! # fn module() {
//! # #[hdl]
//! # let v: Bool = m.input();
//! #[hdl]
//! let my_wire: UInt<8> = wire();
//! #[hdl]
//! if v {
//!     connect(my_wire, 0x45_hdl_u8);
//! } else {
//!     // wires must be connected to under all conditions
//!     connect(my_wire, 0x23_hdl_u8);
//! }
//! # }
//! ```
//!
//! [connection semantics]: crate::_docs::semantics::connection_semantics

#[allow(unused)]
use crate::prelude::*;