fayalite 0.2.0

Hardware Description Language embedded in Rust, using FIRRTL's semantics
Documentation 
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
//! ### Registers
//!
//! Registers are memory devices that will change their state only on a clock
//! edge (or when being reset). They retain their state when not connected to.
//!
//! Registers create a Rust variable with type [`Expr<T>`] where `T` is the type of the register.
//!
//! Registers follow [connection semantics], which are unlike assignments in software, so you should read it.
//!
//! By convention, register names end in `_reg` -- this helps you tell which values are written
//! immediately or on the next clock edge when connecting to them.
//!
//! ```
//! # use fayalite::prelude::*;
//! # #[hdl_module]
//! # fn module() {
//! # #[hdl]
//! # let v: Bool = m.input();
//! #[hdl]
//! let cd: ClockDomain = m.input();
//! #[hdl]
//! let my_reg: UInt<8> = reg_builder().clock_domain(cd).reset(8_hdl_u8);
//! #[hdl]
//! if v {
//!     // my_reg is only changed when both `v` is set and `cd`'s clock edge occurs.
//!     connect(my_reg, 0x45_hdl_u8);
//! }
//! # }
//! ```
//!
//! [connection semantics]: crate::_docs::semantics::connection_semantics

#[allow(unused)]
use crate::expr::Expr;