esp32s2 0.3.0

Peripheral access crate for the ESP32-S2
Documentation 
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#[doc = "Register `APB_PERIPHERAL_1` reader"]
pub struct R(crate::R<APB_PERIPHERAL_1_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<APB_PERIPHERAL_1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<APB_PERIPHERAL_1_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<APB_PERIPHERAL_1_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `APB_PERIPHERAL_1` writer"]
pub struct W(crate::W<APB_PERIPHERAL_1_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<APB_PERIPHERAL_1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<APB_PERIPHERAL_1_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<APB_PERIPHERAL_1_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `APB_PERIPHERAL_SPLIT_BURST` reader - Setting to 1 splits the data phase of the last access and the address phase of following access."]
pub type APB_PERIPHERAL_SPLIT_BURST_R = crate::BitReader<bool>;
#[doc = "Field `APB_PERIPHERAL_SPLIT_BURST` writer - Setting to 1 splits the data phase of the last access and the address phase of following access."]
pub type APB_PERIPHERAL_SPLIT_BURST_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, APB_PERIPHERAL_1_SPEC, bool, O>;
impl R {
    #[doc = "Bit 0 - Setting to 1 splits the data phase of the last access and the address phase of following access."]
    #[inline(always)]
    pub fn apb_peripheral_split_burst(&self) -> APB_PERIPHERAL_SPLIT_BURST_R {
        APB_PERIPHERAL_SPLIT_BURST_R::new((self.bits & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Setting to 1 splits the data phase of the last access and the address phase of following access."]
    #[inline(always)]
    pub fn apb_peripheral_split_burst(&mut self) -> APB_PERIPHERAL_SPLIT_BURST_W<0> {
        APB_PERIPHERAL_SPLIT_BURST_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Peripheral access permission control register 1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb_peripheral_1](index.html) module"]
pub struct APB_PERIPHERAL_1_SPEC;
impl crate::RegisterSpec for APB_PERIPHERAL_1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [apb_peripheral_1::R](R) reader structure"]
impl crate::Readable for APB_PERIPHERAL_1_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb_peripheral_1::W](W) writer structure"]
impl crate::Writable for APB_PERIPHERAL_1_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets APB_PERIPHERAL_1 to value 0x01"]
impl crate::Resettable for APB_PERIPHERAL_1_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0x01
    }
}