#[doc = "Register `SPI_SMEM_DOUT_HEX_MODE` reader"]
pub type R = crate::R<SPI_SMEM_DOUT_HEX_MODE_SPEC>;
#[doc = "Register `SPI_SMEM_DOUT_HEX_MODE` writer"]
pub type W = crate::W<SPI_SMEM_DOUT_HEX_MODE_SPEC>;
#[doc = "Field `SPI_SMEM_DOUT08_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT08_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT08_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT08_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT09_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT09_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT09_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT09_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT10_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT10_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT10_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT10_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT11_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT11_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT11_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT11_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT12_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT12_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT12_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT12_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT13_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT13_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT13_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT13_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT14_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT14_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT14_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT14_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUT15_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT15_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUT15_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUT15_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_SMEM_DOUTS_HEX_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUTS_HEX_MODE_R = crate::BitReader;
#[doc = "Field `SPI_SMEM_DOUTS_HEX_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
pub type SPI_SMEM_DOUTS_HEX_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout08_mode(&self) -> SPI_SMEM_DOUT08_MODE_R {
SPI_SMEM_DOUT08_MODE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout09_mode(&self) -> SPI_SMEM_DOUT09_MODE_R {
SPI_SMEM_DOUT09_MODE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout10_mode(&self) -> SPI_SMEM_DOUT10_MODE_R {
SPI_SMEM_DOUT10_MODE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout11_mode(&self) -> SPI_SMEM_DOUT11_MODE_R {
SPI_SMEM_DOUT11_MODE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout12_mode(&self) -> SPI_SMEM_DOUT12_MODE_R {
SPI_SMEM_DOUT12_MODE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout13_mode(&self) -> SPI_SMEM_DOUT13_MODE_R {
SPI_SMEM_DOUT13_MODE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout14_mode(&self) -> SPI_SMEM_DOUT14_MODE_R {
SPI_SMEM_DOUT14_MODE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dout15_mode(&self) -> SPI_SMEM_DOUT15_MODE_R {
SPI_SMEM_DOUT15_MODE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_douts_hex_mode(&self) -> SPI_SMEM_DOUTS_HEX_MODE_R {
SPI_SMEM_DOUTS_HEX_MODE_R::new(((self.bits >> 8) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI_SMEM_DOUT_HEX_MODE")
.field(
"spi_smem_dout08_mode",
&format_args!("{}", self.spi_smem_dout08_mode().bit()),
)
.field(
"spi_smem_dout09_mode",
&format_args!("{}", self.spi_smem_dout09_mode().bit()),
)
.field(
"spi_smem_dout10_mode",
&format_args!("{}", self.spi_smem_dout10_mode().bit()),
)
.field(
"spi_smem_dout11_mode",
&format_args!("{}", self.spi_smem_dout11_mode().bit()),
)
.field(
"spi_smem_dout12_mode",
&format_args!("{}", self.spi_smem_dout12_mode().bit()),
)
.field(
"spi_smem_dout13_mode",
&format_args!("{}", self.spi_smem_dout13_mode().bit()),
)
.field(
"spi_smem_dout14_mode",
&format_args!("{}", self.spi_smem_dout14_mode().bit()),
)
.field(
"spi_smem_dout15_mode",
&format_args!("{}", self.spi_smem_dout15_mode().bit()),
)
.field(
"spi_smem_douts_hex_mode",
&format_args!("{}", self.spi_smem_douts_hex_mode().bit()),
)
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout08_mode(&mut self) -> SPI_SMEM_DOUT08_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT08_MODE_W::new(self, 0)
}
#[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout09_mode(&mut self) -> SPI_SMEM_DOUT09_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT09_MODE_W::new(self, 1)
}
#[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout10_mode(&mut self) -> SPI_SMEM_DOUT10_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT10_MODE_W::new(self, 2)
}
#[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout11_mode(&mut self) -> SPI_SMEM_DOUT11_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT11_MODE_W::new(self, 3)
}
#[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout12_mode(&mut self) -> SPI_SMEM_DOUT12_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT12_MODE_W::new(self, 4)
}
#[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout13_mode(&mut self) -> SPI_SMEM_DOUT13_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT13_MODE_W::new(self, 5)
}
#[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout14_mode(&mut self) -> SPI_SMEM_DOUT14_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT14_MODE_W::new(self, 6)
}
#[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dout15_mode(&mut self) -> SPI_SMEM_DOUT15_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUT15_MODE_W::new(self, 7)
}
#[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_douts_hex_mode(
&mut self,
) -> SPI_SMEM_DOUTS_HEX_MODE_W<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
SPI_SMEM_DOUTS_HEX_MODE_W::new(self, 8)
}
}
#[doc = "MSPI 16x external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_hex_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_dout_hex_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPI_SMEM_DOUT_HEX_MODE_SPEC;
impl crate::RegisterSpec for SPI_SMEM_DOUT_HEX_MODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi_smem_dout_hex_mode::R`](R) reader structure"]
impl crate::Readable for SPI_SMEM_DOUT_HEX_MODE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`spi_smem_dout_hex_mode::W`](W) writer structure"]
impl crate::Writable for SPI_SMEM_DOUT_HEX_MODE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPI_SMEM_DOUT_HEX_MODE to value 0"]
impl crate::Resettable for SPI_SMEM_DOUT_HEX_MODE_SPEC {
const RESET_VALUE: u32 = 0;
}