#[doc = "Register `SPI_SMEM_DIN_HEX_MODE` reader"]
pub type R = crate::R<SPI_SMEM_DIN_HEX_MODE_SPEC>;
#[doc = "Register `SPI_SMEM_DIN_HEX_MODE` writer"]
pub type W = crate::W<SPI_SMEM_DIN_HEX_MODE_SPEC>;
#[doc = "Field `SPI_SMEM_DIN08_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN08_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN08_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN08_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN09_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN09_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN09_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN09_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN10_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN10_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN10_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN10_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN11_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN11_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN11_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN11_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN12_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN12_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN12_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN12_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN13_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN13_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN13_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN13_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN14_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN14_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN14_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN14_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DIN15_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN15_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DIN15_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DIN15_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SPI_SMEM_DINS_HEX_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DINS_HEX_MODE_R = crate::FieldReader;
#[doc = "Field `SPI_SMEM_DINS_HEX_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
pub type SPI_SMEM_DINS_HEX_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din08_mode(&self) -> SPI_SMEM_DIN08_MODE_R {
SPI_SMEM_DIN08_MODE_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din09_mode(&self) -> SPI_SMEM_DIN09_MODE_R {
SPI_SMEM_DIN09_MODE_R::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din10_mode(&self) -> SPI_SMEM_DIN10_MODE_R {
SPI_SMEM_DIN10_MODE_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din11_mode(&self) -> SPI_SMEM_DIN11_MODE_R {
SPI_SMEM_DIN11_MODE_R::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din12_mode(&self) -> SPI_SMEM_DIN12_MODE_R {
SPI_SMEM_DIN12_MODE_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din13_mode(&self) -> SPI_SMEM_DIN13_MODE_R {
SPI_SMEM_DIN13_MODE_R::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din14_mode(&self) -> SPI_SMEM_DIN14_MODE_R {
SPI_SMEM_DIN14_MODE_R::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_din15_mode(&self) -> SPI_SMEM_DIN15_MODE_R {
SPI_SMEM_DIN15_MODE_R::new(((self.bits >> 21) & 7) as u8)
}
#[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
pub fn spi_smem_dins_hex_mode(&self) -> SPI_SMEM_DINS_HEX_MODE_R {
SPI_SMEM_DINS_HEX_MODE_R::new(((self.bits >> 24) & 7) as u8)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI_SMEM_DIN_HEX_MODE")
.field(
"spi_smem_din08_mode",
&format_args!("{}", self.spi_smem_din08_mode().bits()),
)
.field(
"spi_smem_din09_mode",
&format_args!("{}", self.spi_smem_din09_mode().bits()),
)
.field(
"spi_smem_din10_mode",
&format_args!("{}", self.spi_smem_din10_mode().bits()),
)
.field(
"spi_smem_din11_mode",
&format_args!("{}", self.spi_smem_din11_mode().bits()),
)
.field(
"spi_smem_din12_mode",
&format_args!("{}", self.spi_smem_din12_mode().bits()),
)
.field(
"spi_smem_din13_mode",
&format_args!("{}", self.spi_smem_din13_mode().bits()),
)
.field(
"spi_smem_din14_mode",
&format_args!("{}", self.spi_smem_din14_mode().bits()),
)
.field(
"spi_smem_din15_mode",
&format_args!("{}", self.spi_smem_din15_mode().bits()),
)
.field(
"spi_smem_dins_hex_mode",
&format_args!("{}", self.spi_smem_dins_hex_mode().bits()),
)
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_HEX_MODE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din08_mode(&mut self) -> SPI_SMEM_DIN08_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN08_MODE_W::new(self, 0)
}
#[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din09_mode(&mut self) -> SPI_SMEM_DIN09_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN09_MODE_W::new(self, 3)
}
#[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din10_mode(&mut self) -> SPI_SMEM_DIN10_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN10_MODE_W::new(self, 6)
}
#[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din11_mode(&mut self) -> SPI_SMEM_DIN11_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN11_MODE_W::new(self, 9)
}
#[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din12_mode(&mut self) -> SPI_SMEM_DIN12_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN12_MODE_W::new(self, 12)
}
#[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din13_mode(&mut self) -> SPI_SMEM_DIN13_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN13_MODE_W::new(self, 15)
}
#[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din14_mode(&mut self) -> SPI_SMEM_DIN14_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN14_MODE_W::new(self, 18)
}
#[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_din15_mode(&mut self) -> SPI_SMEM_DIN15_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DIN15_MODE_W::new(self, 21)
}
#[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
#[inline(always)]
#[must_use]
pub fn spi_smem_dins_hex_mode(
&mut self,
) -> SPI_SMEM_DINS_HEX_MODE_W<SPI_SMEM_DIN_HEX_MODE_SPEC> {
SPI_SMEM_DINS_HEX_MODE_W::new(self, 24)
}
}
#[doc = "MSPI 16x external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_hex_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_hex_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPI_SMEM_DIN_HEX_MODE_SPEC;
impl crate::RegisterSpec for SPI_SMEM_DIN_HEX_MODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi_smem_din_hex_mode::R`](R) reader structure"]
impl crate::Readable for SPI_SMEM_DIN_HEX_MODE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`spi_smem_din_hex_mode::W`](W) writer structure"]
impl crate::Writable for SPI_SMEM_DIN_HEX_MODE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPI_SMEM_DIN_HEX_MODE to value 0"]
impl crate::Resettable for SPI_SMEM_DIN_HEX_MODE_SPEC {
const RESET_VALUE: u32 = 0;
}