esp32p4 0.2.0

Peripheral access crate for the ESP32-P4
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163

#[doc = "Register `CMD` reader"]
pub type R = crate::R<CMD_SPEC>;
#[doc = "Register `CMD` writer"]
pub type W = crate::W<CMD_SPEC>;
#[doc = "Field `ICM_REG_AXI_CMD` reader - NA"]
pub type ICM_REG_AXI_CMD_R = crate::FieldReader;
#[doc = "Field `ICM_REG_AXI_CMD` writer - NA"]
pub type ICM_REG_AXI_CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ICM_REG_RD_WR_CHAN` reader - NA"]
pub type ICM_REG_RD_WR_CHAN_R = crate::BitReader;
#[doc = "Field `ICM_REG_RD_WR_CHAN` writer - NA"]
pub type ICM_REG_RD_WR_CHAN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_REG_AXI_MASTER_PORT` reader - NA"]
pub type ICM_REG_AXI_MASTER_PORT_R = crate::FieldReader;
#[doc = "Field `ICM_REG_AXI_MASTER_PORT` writer - NA"]
pub type ICM_REG_AXI_MASTER_PORT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ICM_REG_AXI_ERR_BIT` reader - NA"]
pub type ICM_REG_AXI_ERR_BIT_R = crate::BitReader;
#[doc = "Field `ICM_REG_AXI_SOFT_RESET_BIT` reader - NA"]
pub type ICM_REG_AXI_SOFT_RESET_BIT_R = crate::BitReader;
#[doc = "Field `ICM_REG_AXI_SOFT_RESET_BIT` writer - NA"]
pub type ICM_REG_AXI_SOFT_RESET_BIT_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_REG_AXI_RD_WR_CMD` reader - NA"]
pub type ICM_REG_AXI_RD_WR_CMD_R = crate::BitReader;
#[doc = "Field `ICM_REG_AXI_RD_WR_CMD` writer - NA"]
pub type ICM_REG_AXI_RD_WR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ICM_REG_AXI_CMD_EN` reader - NA"]
pub type ICM_REG_AXI_CMD_EN_R = crate::BitReader;
#[doc = "Field `ICM_REG_AXI_CMD_EN` writer - NA"]
pub type ICM_REG_AXI_CMD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bits 0:2 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_cmd(&self) -> ICM_REG_AXI_CMD_R {
        ICM_REG_AXI_CMD_R::new((self.bits & 7) as u8)
    }
    #[doc = "Bit 7 - NA"]
    #[inline(always)]
    pub fn icm_reg_rd_wr_chan(&self) -> ICM_REG_RD_WR_CHAN_R {
        ICM_REG_RD_WR_CHAN_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bits 8:11 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_master_port(&self) -> ICM_REG_AXI_MASTER_PORT_R {
        ICM_REG_AXI_MASTER_PORT_R::new(((self.bits >> 8) & 0x0f) as u8)
    }
    #[doc = "Bit 28 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_err_bit(&self) -> ICM_REG_AXI_ERR_BIT_R {
        ICM_REG_AXI_ERR_BIT_R::new(((self.bits >> 28) & 1) != 0)
    }
    #[doc = "Bit 29 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_soft_reset_bit(&self) -> ICM_REG_AXI_SOFT_RESET_BIT_R {
        ICM_REG_AXI_SOFT_RESET_BIT_R::new(((self.bits >> 29) & 1) != 0)
    }
    #[doc = "Bit 30 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_rd_wr_cmd(&self) -> ICM_REG_AXI_RD_WR_CMD_R {
        ICM_REG_AXI_RD_WR_CMD_R::new(((self.bits >> 30) & 1) != 0)
    }
    #[doc = "Bit 31 - NA"]
    #[inline(always)]
    pub fn icm_reg_axi_cmd_en(&self) -> ICM_REG_AXI_CMD_EN_R {
        ICM_REG_AXI_CMD_EN_R::new(((self.bits >> 31) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CMD")
            .field(
                "icm_reg_axi_cmd",
                &format_args!("{}", self.icm_reg_axi_cmd().bits()),
            )
            .field(
                "icm_reg_rd_wr_chan",
                &format_args!("{}", self.icm_reg_rd_wr_chan().bit()),
            )
            .field(
                "icm_reg_axi_master_port",
                &format_args!("{}", self.icm_reg_axi_master_port().bits()),
            )
            .field(
                "icm_reg_axi_err_bit",
                &format_args!("{}", self.icm_reg_axi_err_bit().bit()),
            )
            .field(
                "icm_reg_axi_soft_reset_bit",
                &format_args!("{}", self.icm_reg_axi_soft_reset_bit().bit()),
            )
            .field(
                "icm_reg_axi_rd_wr_cmd",
                &format_args!("{}", self.icm_reg_axi_rd_wr_cmd().bit()),
            )
            .field(
                "icm_reg_axi_cmd_en",
                &format_args!("{}", self.icm_reg_axi_cmd_en().bit()),
            )
            .finish()
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        core::fmt::Debug::fmt(&self.read(), f)
    }
}
impl W {
    #[doc = "Bits 0:2 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_axi_cmd(&mut self) -> ICM_REG_AXI_CMD_W<CMD_SPEC> {
        ICM_REG_AXI_CMD_W::new(self, 0)
    }
    #[doc = "Bit 7 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_rd_wr_chan(&mut self) -> ICM_REG_RD_WR_CHAN_W<CMD_SPEC> {
        ICM_REG_RD_WR_CHAN_W::new(self, 7)
    }
    #[doc = "Bits 8:11 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_axi_master_port(&mut self) -> ICM_REG_AXI_MASTER_PORT_W<CMD_SPEC> {
        ICM_REG_AXI_MASTER_PORT_W::new(self, 8)
    }
    #[doc = "Bit 29 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_axi_soft_reset_bit(&mut self) -> ICM_REG_AXI_SOFT_RESET_BIT_W<CMD_SPEC> {
        ICM_REG_AXI_SOFT_RESET_BIT_W::new(self, 29)
    }
    #[doc = "Bit 30 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_axi_rd_wr_cmd(&mut self) -> ICM_REG_AXI_RD_WR_CMD_W<CMD_SPEC> {
        ICM_REG_AXI_RD_WR_CMD_W::new(self, 30)
    }
    #[doc = "Bit 31 - NA"]
    #[inline(always)]
    #[must_use]
    pub fn icm_reg_axi_cmd_en(&mut self) -> ICM_REG_AXI_CMD_EN_W<CMD_SPEC> {
        ICM_REG_AXI_CMD_EN_W::new(self, 31)
    }
}
#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMD_SPEC;
impl crate::RegisterSpec for CMD_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
impl crate::Readable for CMD_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
impl crate::Writable for CMD_SPEC {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMD to value 0"]
impl crate::Resettable for CMD_SPEC {
    const RESET_VALUE: u32 = 0;
}