#[doc = "Register `CTRL` reader"]
pub type R = crate::R<CTRL_SPEC>;
#[doc = "Register `CTRL` writer"]
pub type W = crate::W<CTRL_SPEC>;
#[doc = "Field `FDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
pub type FDUMMY_RIN_R = crate::BitReader;
#[doc = "Field `FDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
pub type FDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
pub type FDUMMY_WOUT_R = crate::BitReader;
#[doc = "Field `FDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
pub type FDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FDOUT_OCT` reader - Apply 8 signals during write-data phase 1:enable 0: disable"]
pub type FDOUT_OCT_R = crate::BitReader;
#[doc = "Field `FDIN_OCT` reader - Apply 8 signals during read-data phase 1:enable 0: disable"]
pub type FDIN_OCT_R = crate::BitReader;
#[doc = "Field `FADDR_OCT` reader - Apply 8 signals during address phase 1:enable 0: disable"]
pub type FADDR_OCT_R = crate::BitReader;
#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"]
pub type FCMD_QUAD_R = crate::BitReader;
#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"]
pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable"]
pub type FCMD_OCT_R = crate::BitReader;
#[doc = "Field `FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
pub type FCS_CRC_EN_R = crate::BitReader;
#[doc = "Field `TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
pub type TX_CRC_EN_R = crate::BitReader;
#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
pub type FASTRD_MODE_R = crate::BitReader;
#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
pub type FREAD_DUAL_R = crate::BitReader;
#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
pub type RESANDRES_R = crate::BitReader;
#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
pub type Q_POL_R = crate::BitReader;
#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
pub type D_POL_R = crate::BitReader;
#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
pub type FREAD_QUAD_R = crate::BitReader;
#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
pub type WP_R = crate::BitReader;
#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
pub type WRSR_2B_R = crate::BitReader;
#[doc = "Field `WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
pub type FREAD_DIO_R = crate::BitReader;
#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
pub type FREAD_QIO_R = crate::BitReader;
#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
#[inline(always)]
pub fn fdummy_rin(&self) -> FDUMMY_RIN_R {
FDUMMY_RIN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
#[inline(always)]
pub fn fdummy_wout(&self) -> FDUMMY_WOUT_R {
FDUMMY_WOUT_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"]
#[inline(always)]
pub fn fdout_oct(&self) -> FDOUT_OCT_R {
FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"]
#[inline(always)]
pub fn fdin_oct(&self) -> FDIN_OCT_R {
FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"]
#[inline(always)]
pub fn faddr_oct(&self) -> FADDR_OCT_R {
FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
#[inline(always)]
pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"]
#[inline(always)]
pub fn fcmd_oct(&self) -> FCMD_OCT_R {
FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
#[inline(always)]
pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
#[inline(always)]
pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
#[inline(always)]
pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_dual(&self) -> FREAD_DUAL_R {
FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
#[inline(always)]
pub fn resandres(&self) -> RESANDRES_R {
RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
#[inline(always)]
pub fn q_pol(&self) -> Q_POL_R {
Q_POL_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
#[inline(always)]
pub fn d_pol(&self) -> D_POL_R {
D_POL_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_quad(&self) -> FREAD_QUAD_R {
FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
#[inline(always)]
pub fn wp(&self) -> WP_R {
WP_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
#[inline(always)]
pub fn wrsr_2b(&self) -> WRSR_2B_R {
WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_dio(&self) -> FREAD_DIO_R {
FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_qio(&self) -> FREAD_QIO_R {
FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CTRL")
.field("fdummy_rin", &self.fdummy_rin())
.field("fdummy_wout", &self.fdummy_wout())
.field("fdout_oct", &self.fdout_oct())
.field("fdin_oct", &self.fdin_oct())
.field("faddr_oct", &self.faddr_oct())
.field("fcmd_quad", &self.fcmd_quad())
.field("fcmd_oct", &self.fcmd_oct())
.field("fcs_crc_en", &self.fcs_crc_en())
.field("tx_crc_en", &self.tx_crc_en())
.field("fastrd_mode", &self.fastrd_mode())
.field("fread_dual", &self.fread_dual())
.field("resandres", &self.resandres())
.field("q_pol", &self.q_pol())
.field("d_pol", &self.d_pol())
.field("fread_quad", &self.fread_quad())
.field("wp", &self.wp())
.field("wrsr_2b", &self.wrsr_2b())
.field("fread_dio", &self.fread_dio())
.field("fread_qio", &self.fread_qio())
.finish()
}
}
impl W {
#[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
#[inline(always)]
pub fn fdummy_rin(&mut self) -> FDUMMY_RIN_W<CTRL_SPEC> {
FDUMMY_RIN_W::new(self, 2)
}
#[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
#[inline(always)]
pub fn fdummy_wout(&mut self) -> FDUMMY_WOUT_W<CTRL_SPEC> {
FDUMMY_WOUT_W::new(self, 3)
}
#[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
#[inline(always)]
pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
FCMD_QUAD_W::new(self, 8)
}
#[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
#[inline(always)]
pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
FASTRD_MODE_W::new(self, 13)
}
#[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
FREAD_DUAL_W::new(self, 14)
}
#[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
#[inline(always)]
pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
RESANDRES_W::new(self, 15)
}
#[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
#[inline(always)]
pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
Q_POL_W::new(self, 18)
}
#[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
#[inline(always)]
pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
D_POL_W::new(self, 19)
}
#[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
FREAD_QUAD_W::new(self, 20)
}
#[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
#[inline(always)]
pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
WP_W::new(self, 21)
}
#[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
#[inline(always)]
pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
WRSR_2B_W::new(self, 22)
}
#[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
FREAD_DIO_W::new(self, 23)
}
#[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
#[inline(always)]
pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
FREAD_QIO_W::new(self, 24)
}
}
#[doc = "SPI1 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRL_SPEC;
impl crate::RegisterSpec for CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate::Readable for CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CTRL_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRL to value 0x002c_a00c"]
impl crate::Resettable for CTRL_SPEC {
const RESET_VALUE: u32 = 0x002c_a00c;
}