esp32c5 0.2.2

Peripheral access crate for the ESP32-C5
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

#[doc = "Register `CACHE_ACS_CNT_INT_ENA` reader"]
pub type R = crate::R<CACHE_ACS_CNT_INT_ENA_SPEC>;
#[doc = "Register `CACHE_ACS_CNT_INT_ENA` writer"]
pub type W = crate::W<CACHE_ACS_CNT_INT_ENA_SPEC>;
#[doc = "Field `IBUS2_OVF_INT_ENA` reader - Reserved"]
pub type IBUS2_OVF_INT_ENA_R = crate::BitReader;
#[doc = "Field `IBUS2_OVF_INT_ENA` writer - Reserved"]
pub type IBUS2_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBUS3_OVF_INT_ENA` reader - Reserved"]
pub type IBUS3_OVF_INT_ENA_R = crate::BitReader;
#[doc = "Field `IBUS3_OVF_INT_ENA` writer - Reserved"]
pub type IBUS3_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BUS0_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus0 accesses DCache."]
pub type BUS0_OVF_INT_ENA_R = crate::BitReader;
#[doc = "Field `BUS0_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus0 accesses DCache."]
pub type BUS0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BUS1_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus1 accesses DCache."]
pub type BUS1_OVF_INT_ENA_R = crate::BitReader;
#[doc = "Field `BUS1_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus1 accesses DCache."]
pub type BUS1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 2 - Reserved"]
    #[inline(always)]
    pub fn ibus2_ovf_int_ena(&self) -> IBUS2_OVF_INT_ENA_R {
        IBUS2_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Reserved"]
    #[inline(always)]
    pub fn ibus3_ovf_int_ena(&self) -> IBUS3_OVF_INT_ENA_R {
        IBUS3_OVF_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus0 accesses DCache."]
    #[inline(always)]
    pub fn bus0_ovf_int_ena(&self) -> BUS0_OVF_INT_ENA_R {
        BUS0_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus1 accesses DCache."]
    #[inline(always)]
    pub fn bus1_ovf_int_ena(&self) -> BUS1_OVF_INT_ENA_R {
        BUS1_OVF_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CACHE_ACS_CNT_INT_ENA")
            .field("ibus2_ovf_int_ena", &self.ibus2_ovf_int_ena())
            .field("ibus3_ovf_int_ena", &self.ibus3_ovf_int_ena())
            .field("bus0_ovf_int_ena", &self.bus0_ovf_int_ena())
            .field("bus1_ovf_int_ena", &self.bus1_ovf_int_ena())
            .finish()
    }
}
impl W {
    #[doc = "Bit 2 - Reserved"]
    #[inline(always)]
    pub fn ibus2_ovf_int_ena(&mut self) -> IBUS2_OVF_INT_ENA_W<'_, CACHE_ACS_CNT_INT_ENA_SPEC> {
        IBUS2_OVF_INT_ENA_W::new(self, 2)
    }
    #[doc = "Bit 3 - Reserved"]
    #[inline(always)]
    pub fn ibus3_ovf_int_ena(&mut self) -> IBUS3_OVF_INT_ENA_W<'_, CACHE_ACS_CNT_INT_ENA_SPEC> {
        IBUS3_OVF_INT_ENA_W::new(self, 3)
    }
    #[doc = "Bit 4 - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus0 accesses DCache."]
    #[inline(always)]
    pub fn bus0_ovf_int_ena(&mut self) -> BUS0_OVF_INT_ENA_W<'_, CACHE_ACS_CNT_INT_ENA_SPEC> {
        BUS0_OVF_INT_ENA_W::new(self, 4)
    }
    #[doc = "Bit 5 - The bit is used to enable interrupt of one of counters overflow that occurs in DCache due to bus1 accesses DCache."]
    #[inline(always)]
    pub fn bus1_ovf_int_ena(&mut self) -> BUS1_OVF_INT_ENA_W<'_, CACHE_ACS_CNT_INT_ENA_SPEC> {
        BUS1_OVF_INT_ENA_W::new(self, 5)
    }
}
#[doc = "Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_acs_cnt_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_acs_cnt_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CACHE_ACS_CNT_INT_ENA_SPEC;
impl crate::RegisterSpec for CACHE_ACS_CNT_INT_ENA_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`cache_acs_cnt_int_ena::R`](R) reader structure"]
impl crate::Readable for CACHE_ACS_CNT_INT_ENA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cache_acs_cnt_int_ena::W`](W) writer structure"]
impl crate::Writable for CACHE_ACS_CNT_INT_ENA_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CACHE_ACS_CNT_INT_ENA to value 0"]
impl crate::Resettable for CACHE_ACS_CNT_INT_ENA_SPEC {}