esp32c5 0.2.2

Peripheral access crate for the ESP32-C5
Documentation 
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#[doc = "Register `CACHE_CTRL` reader"]
pub type R = crate::R<CACHE_CTRL_SPEC>;
#[doc = "Register `CACHE_CTRL` writer"]
pub type W = crate::W<CACHE_CTRL_SPEC>;
#[doc = "Field `CACHE_SHUT_BUS0` reader - The bit is used to disable core0 bus0 access Cache, 0: enable, 1: disable"]
pub type CACHE_SHUT_BUS0_R = crate::BitReader;
#[doc = "Field `CACHE_SHUT_BUS0` writer - The bit is used to disable core0 bus0 access Cache, 0: enable, 1: disable"]
pub type CACHE_SHUT_BUS0_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CACHE_SHUT_BUS1` reader - The bit is used to disable core0 bus1 access Cache, 0: enable, 1: disable"]
pub type CACHE_SHUT_BUS1_R = crate::BitReader;
#[doc = "Field `CACHE_SHUT_BUS1` writer - The bit is used to disable core0 bus1 access Cache, 0: enable, 1: disable"]
pub type CACHE_SHUT_BUS1_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - The bit is used to disable core0 bus0 access Cache, 0: enable, 1: disable"]
    #[inline(always)]
    pub fn cache_shut_bus0(&self) -> CACHE_SHUT_BUS0_R {
        CACHE_SHUT_BUS0_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - The bit is used to disable core0 bus1 access Cache, 0: enable, 1: disable"]
    #[inline(always)]
    pub fn cache_shut_bus1(&self) -> CACHE_SHUT_BUS1_R {
        CACHE_SHUT_BUS1_R::new(((self.bits >> 1) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CACHE_CTRL")
            .field("cache_shut_bus0", &self.cache_shut_bus0())
            .field("cache_shut_bus1", &self.cache_shut_bus1())
            .finish()
    }
}
impl W {
    #[doc = "Bit 0 - The bit is used to disable core0 bus0 access Cache, 0: enable, 1: disable"]
    #[inline(always)]
    pub fn cache_shut_bus0(&mut self) -> CACHE_SHUT_BUS0_W<'_, CACHE_CTRL_SPEC> {
        CACHE_SHUT_BUS0_W::new(self, 0)
    }
    #[doc = "Bit 1 - The bit is used to disable core0 bus1 access Cache, 0: enable, 1: disable"]
    #[inline(always)]
    pub fn cache_shut_bus1(&mut self) -> CACHE_SHUT_BUS1_W<'_, CACHE_CTRL_SPEC> {
        CACHE_SHUT_BUS1_W::new(self, 1)
    }
}
#[doc = "Data cache control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CACHE_CTRL_SPEC;
impl crate::RegisterSpec for CACHE_CTRL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`cache_ctrl::R`](R) reader structure"]
impl crate::Readable for CACHE_CTRL_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cache_ctrl::W`](W) writer structure"]
impl crate::Writable for CACHE_CTRL_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CACHE_CTRL to value 0"]
impl crate::Resettable for CACHE_CTRL_SPEC {}