Type Alias esp32c3::spi2::ctrl::W

pub type W = W<CTRL_SPEC>;

Register CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn dummy_out(&mut self) -> DUMMY_OUT_W<'_, CTRL_SPEC>

Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.

pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, CTRL_SPEC>

Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, CTRL_SPEC>

Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<'_, CTRL_SPEC>

Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<'_, CTRL_SPEC>

Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fread_dual(&mut self) -> FREAD_DUAL_W<'_, CTRL_SPEC>

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.

pub fn fread_quad(&mut self) -> FREAD_QUAD_W<'_, CTRL_SPEC>

Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.

pub fn q_pol(&mut self) -> Q_POL_W<'_, CTRL_SPEC>

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.

pub fn d_pol(&mut self) -> D_POL_W<'_, CTRL_SPEC>

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.

pub fn hold_pol(&mut self) -> HOLD_POL_W<'_, CTRL_SPEC>

Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

pub fn wp_pol(&mut self) -> WP_POL_W<'_, CTRL_SPEC>

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<'_, CTRL_SPEC>

Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.

pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<'_, CTRL_SPEC>

Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.