1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `DUMMY_OUT` reader - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
6pub type DUMMY_OUT_R = crate::BitReader;
7#[doc = "Field `DUMMY_OUT` writer - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
8pub type DUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FADDR_DUAL` reader - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
10pub type FADDR_DUAL_R = crate::BitReader;
11#[doc = "Field `FADDR_DUAL` writer - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
12pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FADDR_QUAD` reader - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
14pub type FADDR_QUAD_R = crate::BitReader;
15#[doc = "Field `FADDR_QUAD` writer - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
16pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
18pub type FCMD_DUAL_R = crate::BitReader;
19#[doc = "Field `FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
20pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
22pub type FCMD_QUAD_R = crate::BitReader;
23#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
24pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
26pub type FREAD_DUAL_R = crate::BitReader;
27#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
28pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
30pub type FREAD_QUAD_R = crate::BitReader;
31#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
32pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
34pub type Q_POL_R = crate::BitReader;
35#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
36pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
38pub type D_POL_R = crate::BitReader;
39#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
40pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `HOLD_POL` reader - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
42pub type HOLD_POL_R = crate::BitReader;
43#[doc = "Field `HOLD_POL` writer - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
44pub type HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `WP_POL` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
46pub type WP_POL_R = crate::BitReader;
47#[doc = "Field `WP_POL` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
48pub type WP_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
50pub type RD_BIT_ORDER_R = crate::BitReader;
51#[doc = "Field `RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
52pub type RD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
54pub type WR_BIT_ORDER_R = crate::BitReader;
55#[doc = "Field `WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
56pub type WR_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
59 #[inline(always)]
60 pub fn dummy_out(&self) -> DUMMY_OUT_R {
61 DUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
62 }
63 #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
64 #[inline(always)]
65 pub fn faddr_dual(&self) -> FADDR_DUAL_R {
66 FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
69 #[inline(always)]
70 pub fn faddr_quad(&self) -> FADDR_QUAD_R {
71 FADDR_QUAD_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
74 #[inline(always)]
75 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
76 FCMD_DUAL_R::new(((self.bits >> 8) & 1) != 0)
77 }
78 #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
79 #[inline(always)]
80 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
81 FCMD_QUAD_R::new(((self.bits >> 9) & 1) != 0)
82 }
83 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
84 #[inline(always)]
85 pub fn fread_dual(&self) -> FREAD_DUAL_R {
86 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
87 }
88 #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
89 #[inline(always)]
90 pub fn fread_quad(&self) -> FREAD_QUAD_R {
91 FREAD_QUAD_R::new(((self.bits >> 15) & 1) != 0)
92 }
93 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
94 #[inline(always)]
95 pub fn q_pol(&self) -> Q_POL_R {
96 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
97 }
98 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
99 #[inline(always)]
100 pub fn d_pol(&self) -> D_POL_R {
101 D_POL_R::new(((self.bits >> 19) & 1) != 0)
102 }
103 #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
104 #[inline(always)]
105 pub fn hold_pol(&self) -> HOLD_POL_R {
106 HOLD_POL_R::new(((self.bits >> 20) & 1) != 0)
107 }
108 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
109 #[inline(always)]
110 pub fn wp_pol(&self) -> WP_POL_R {
111 WP_POL_R::new(((self.bits >> 21) & 1) != 0)
112 }
113 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
114 #[inline(always)]
115 pub fn rd_bit_order(&self) -> RD_BIT_ORDER_R {
116 RD_BIT_ORDER_R::new(((self.bits >> 25) & 1) != 0)
117 }
118 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
119 #[inline(always)]
120 pub fn wr_bit_order(&self) -> WR_BIT_ORDER_R {
121 WR_BIT_ORDER_R::new(((self.bits >> 26) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("CTRL")
128 .field("dummy_out", &self.dummy_out())
129 .field("faddr_dual", &self.faddr_dual())
130 .field("faddr_quad", &self.faddr_quad())
131 .field("fcmd_dual", &self.fcmd_dual())
132 .field("fcmd_quad", &self.fcmd_quad())
133 .field("fread_dual", &self.fread_dual())
134 .field("fread_quad", &self.fread_quad())
135 .field("q_pol", &self.q_pol())
136 .field("d_pol", &self.d_pol())
137 .field("hold_pol", &self.hold_pol())
138 .field("wp_pol", &self.wp_pol())
139 .field("rd_bit_order", &self.rd_bit_order())
140 .field("wr_bit_order", &self.wr_bit_order())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
146 #[inline(always)]
147 pub fn dummy_out(&mut self) -> DUMMY_OUT_W<CTRL_SPEC> {
148 DUMMY_OUT_W::new(self, 3)
149 }
150 #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
151 #[inline(always)]
152 pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CTRL_SPEC> {
153 FADDR_DUAL_W::new(self, 5)
154 }
155 #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
156 #[inline(always)]
157 pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CTRL_SPEC> {
158 FADDR_QUAD_W::new(self, 6)
159 }
160 #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
161 #[inline(always)]
162 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
163 FCMD_DUAL_W::new(self, 8)
164 }
165 #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
166 #[inline(always)]
167 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
168 FCMD_QUAD_W::new(self, 9)
169 }
170 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
171 #[inline(always)]
172 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
173 FREAD_DUAL_W::new(self, 14)
174 }
175 #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
176 #[inline(always)]
177 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
178 FREAD_QUAD_W::new(self, 15)
179 }
180 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
181 #[inline(always)]
182 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
183 Q_POL_W::new(self, 18)
184 }
185 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
186 #[inline(always)]
187 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
188 D_POL_W::new(self, 19)
189 }
190 #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
191 #[inline(always)]
192 pub fn hold_pol(&mut self) -> HOLD_POL_W<CTRL_SPEC> {
193 HOLD_POL_W::new(self, 20)
194 }
195 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
196 #[inline(always)]
197 pub fn wp_pol(&mut self) -> WP_POL_W<CTRL_SPEC> {
198 WP_POL_W::new(self, 21)
199 }
200 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
201 #[inline(always)]
202 pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
203 RD_BIT_ORDER_W::new(self, 25)
204 }
205 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
206 #[inline(always)]
207 pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
208 WR_BIT_ORDER_W::new(self, 26)
209 }
210}
211#[doc = "SPI control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct CTRL_SPEC;
213impl crate::RegisterSpec for CTRL_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
217impl crate::Readable for CTRL_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
219impl crate::Writable for CTRL_SPEC {
220 type Safety = crate::Unsafe;
221 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223}
224#[doc = "`reset()` method sets CTRL to value 0x003c_0000"]
225impl crate::Resettable for CTRL_SPEC {
226 const RESET_VALUE: u32 = 0x003c_0000;
227}