Type Alias esp32c3::spi1::ctrl::R

pub type R = R<CTRL_SPEC>;

Register CTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn fdummy_out(&self) -> FDUMMY_OUT_R

Bit 3 - In the dummy phase the signal level of spi is output by the spi controller.

pub fn fcmd_dual(&self) -> FCMD_DUAL_R

Bit 7 - Apply 2 signals during command phase 1:enable 0: disable

pub fn fcmd_quad(&self) -> FCMD_QUAD_R

Bit 8 - Apply 4 signals during command phase 1:enable 0: disable

pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R

Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.

pub fn tx_crc_en(&self) -> TX_CRC_EN_R

Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable

pub fn fastrd_mode(&self) -> FASTRD_MODE_R

Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.

pub fn fread_dual(&self) -> FREAD_DUAL_R

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

pub fn resandres(&self) -> RESANDRES_R

Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.

pub fn q_pol(&self) -> Q_POL_R

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

pub fn d_pol(&self) -> D_POL_R

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

pub fn fread_quad(&self) -> FREAD_QUAD_R

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

pub fn wp(&self) -> WP_R

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

pub fn wrsr_2b(&self) -> WRSR_2B_R

Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable.

pub fn fread_dio(&self) -> FREAD_DIO_R

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

pub fn fread_qio(&self) -> FREAD_QIO_R

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.