1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FDUMMY_OUT` reader - In the dummy phase the signal level of spi is output by the spi controller."]
6pub type FDUMMY_OUT_R = crate::BitReader;
7#[doc = "Field `FDUMMY_OUT` writer - In the dummy phase the signal level of spi is output by the spi controller."]
8pub type FDUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable"]
10pub type FCMD_DUAL_R = crate::BitReader;
11#[doc = "Field `FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable"]
12pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"]
14pub type FCMD_QUAD_R = crate::BitReader;
15#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"]
16pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
18pub type FCS_CRC_EN_R = crate::BitReader;
19#[doc = "Field `FCS_CRC_EN` writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
20pub type FCS_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
22pub type TX_CRC_EN_R = crate::BitReader;
23#[doc = "Field `TX_CRC_EN` writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
24pub type TX_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
26pub type FASTRD_MODE_R = crate::BitReader;
27#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
28pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
30pub type FREAD_DUAL_R = crate::BitReader;
31#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
32pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
34pub type RESANDRES_R = crate::BitReader;
35#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
36pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
38pub type Q_POL_R = crate::BitReader;
39#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
40pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
42pub type D_POL_R = crate::BitReader;
43#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
44pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
46pub type FREAD_QUAD_R = crate::BitReader;
47#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
48pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
50pub type WP_R = crate::BitReader;
51#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
52pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
54pub type WRSR_2B_R = crate::BitReader;
55#[doc = "Field `WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
56pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
58pub type FREAD_DIO_R = crate::BitReader;
59#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
60pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
62pub type FREAD_QIO_R = crate::BitReader;
63#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
64pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
67 #[inline(always)]
68 pub fn fdummy_out(&self) -> FDUMMY_OUT_R {
69 FDUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
70 }
71 #[doc = "Bit 7 - Apply 2 signals during command phase 1:enable 0: disable"]
72 #[inline(always)]
73 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
74 FCMD_DUAL_R::new(((self.bits >> 7) & 1) != 0)
75 }
76 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
77 #[inline(always)]
78 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
79 FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
82 #[inline(always)]
83 pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
84 FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
85 }
86 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
87 #[inline(always)]
88 pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
89 TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
90 }
91 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
92 #[inline(always)]
93 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
94 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
95 }
96 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
97 #[inline(always)]
98 pub fn fread_dual(&self) -> FREAD_DUAL_R {
99 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
100 }
101 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
102 #[inline(always)]
103 pub fn resandres(&self) -> RESANDRES_R {
104 RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
105 }
106 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
107 #[inline(always)]
108 pub fn q_pol(&self) -> Q_POL_R {
109 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
110 }
111 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
112 #[inline(always)]
113 pub fn d_pol(&self) -> D_POL_R {
114 D_POL_R::new(((self.bits >> 19) & 1) != 0)
115 }
116 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
117 #[inline(always)]
118 pub fn fread_quad(&self) -> FREAD_QUAD_R {
119 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
120 }
121 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
122 #[inline(always)]
123 pub fn wp(&self) -> WP_R {
124 WP_R::new(((self.bits >> 21) & 1) != 0)
125 }
126 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
127 #[inline(always)]
128 pub fn wrsr_2b(&self) -> WRSR_2B_R {
129 WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
130 }
131 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
132 #[inline(always)]
133 pub fn fread_dio(&self) -> FREAD_DIO_R {
134 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
135 }
136 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
137 #[inline(always)]
138 pub fn fread_qio(&self) -> FREAD_QIO_R {
139 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("CTRL")
146 .field("fdummy_out", &self.fdummy_out())
147 .field("fcmd_dual", &self.fcmd_dual())
148 .field("fcmd_quad", &self.fcmd_quad())
149 .field("fcs_crc_en", &self.fcs_crc_en())
150 .field("tx_crc_en", &self.tx_crc_en())
151 .field("fastrd_mode", &self.fastrd_mode())
152 .field("fread_dual", &self.fread_dual())
153 .field("resandres", &self.resandres())
154 .field("q_pol", &self.q_pol())
155 .field("d_pol", &self.d_pol())
156 .field("fread_quad", &self.fread_quad())
157 .field("wp", &self.wp())
158 .field("wrsr_2b", &self.wrsr_2b())
159 .field("fread_dio", &self.fread_dio())
160 .field("fread_qio", &self.fread_qio())
161 .finish()
162 }
163}
164impl W {
165 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
166 #[inline(always)]
167 pub fn fdummy_out(&mut self) -> FDUMMY_OUT_W<CTRL_SPEC> {
168 FDUMMY_OUT_W::new(self, 3)
169 }
170 #[doc = "Bit 7 - Apply 2 signals during command phase 1:enable 0: disable"]
171 #[inline(always)]
172 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
173 FCMD_DUAL_W::new(self, 7)
174 }
175 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
176 #[inline(always)]
177 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
178 FCMD_QUAD_W::new(self, 8)
179 }
180 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
181 #[inline(always)]
182 pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
183 FCS_CRC_EN_W::new(self, 10)
184 }
185 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
186 #[inline(always)]
187 pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
188 TX_CRC_EN_W::new(self, 11)
189 }
190 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
191 #[inline(always)]
192 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
193 FASTRD_MODE_W::new(self, 13)
194 }
195 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
196 #[inline(always)]
197 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
198 FREAD_DUAL_W::new(self, 14)
199 }
200 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
201 #[inline(always)]
202 pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
203 RESANDRES_W::new(self, 15)
204 }
205 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
206 #[inline(always)]
207 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
208 Q_POL_W::new(self, 18)
209 }
210 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
211 #[inline(always)]
212 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
213 D_POL_W::new(self, 19)
214 }
215 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
216 #[inline(always)]
217 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
218 FREAD_QUAD_W::new(self, 20)
219 }
220 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
221 #[inline(always)]
222 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
223 WP_W::new(self, 21)
224 }
225 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
226 #[inline(always)]
227 pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
228 WRSR_2B_W::new(self, 22)
229 }
230 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
231 #[inline(always)]
232 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
233 FREAD_DIO_W::new(self, 23)
234 }
235 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
236 #[inline(always)]
237 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
238 FREAD_QIO_W::new(self, 24)
239 }
240}
241#[doc = "SPI1 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
242pub struct CTRL_SPEC;
243impl crate::RegisterSpec for CTRL_SPEC {
244 type Ux = u32;
245}
246#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
247impl crate::Readable for CTRL_SPEC {}
248#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
249impl crate::Writable for CTRL_SPEC {
250 type Safety = crate::Unsafe;
251 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
252 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
253}
254#[doc = "`reset()` method sets CTRL to value 0x002c_a000"]
255impl crate::Resettable for CTRL_SPEC {
256 const RESET_VALUE: u32 = 0x002c_a000;
257}