#[doc = "Register `DOUT_MODE` reader"]
pub struct R(crate::R<DOUT_MODE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DOUT_MODE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DOUT_MODE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DOUT_MODE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DOUT_MODE` writer"]
pub struct W(crate::W<DOUT_MODE_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DOUT_MODE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DOUT_MODE_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DOUT_MODE_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT0_MODE_R(crate::FieldReader<bool, bool>);
impl DOUT0_MODE_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DOUT0_MODE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DOUT0_MODE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DOUT0_MODE` writer - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT0_MODE_W<'a> {
w: &'a mut W,
}
impl<'a> DOUT0_MODE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !1) | (value as u32 & 1);
self.w
}
}
#[doc = "Field `DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT1_MODE_R(crate::FieldReader<bool, bool>);
impl DOUT1_MODE_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DOUT1_MODE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DOUT1_MODE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DOUT1_MODE` writer - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT1_MODE_W<'a> {
w: &'a mut W,
}
impl<'a> DOUT1_MODE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 1)) | ((value as u32 & 1) << 1);
self.w
}
}
#[doc = "Field `DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT2_MODE_R(crate::FieldReader<bool, bool>);
impl DOUT2_MODE_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DOUT2_MODE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DOUT2_MODE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DOUT2_MODE` writer - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT2_MODE_W<'a> {
w: &'a mut W,
}
impl<'a> DOUT2_MODE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 2)) | ((value as u32 & 1) << 2);
self.w
}
}
#[doc = "Field `DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT3_MODE_R(crate::FieldReader<bool, bool>);
impl DOUT3_MODE_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DOUT3_MODE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DOUT3_MODE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DOUT3_MODE` writer - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
pub struct DOUT3_MODE_W<'a> {
w: &'a mut W,
}
impl<'a> DOUT3_MODE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 3)) | ((value as u32 & 1) << 3);
self.w
}
}
impl R {
#[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout0_mode(&self) -> DOUT0_MODE_R {
DOUT0_MODE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout1_mode(&self) -> DOUT1_MODE_R {
DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout2_mode(&self) -> DOUT2_MODE_R {
DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout3_mode(&self) -> DOUT3_MODE_R {
DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout0_mode(&mut self) -> DOUT0_MODE_W {
DOUT0_MODE_W { w: self }
}
#[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout1_mode(&mut self) -> DOUT1_MODE_W {
DOUT1_MODE_W { w: self }
}
#[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout2_mode(&mut self) -> DOUT2_MODE_W {
DOUT2_MODE_W { w: self }
}
#[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
#[inline(always)]
pub fn dout3_mode(&mut self) -> DOUT3_MODE_W {
DOUT3_MODE_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SPI output delay mode configuration\n\nThis register you can [`read`]
(crate::generic::Reg::read), [`write_with_zero`]
(crate::generic::Reg::write_with_zero), [`reset`]
(crate::generic::Reg::reset), [`write`]
(crate::generic::Reg::write), [`modify`]
(crate::generic::Reg::modify). See [API]
(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dout_mode]
(index.html) module"]
pub struct DOUT_MODE_SPEC;
impl crate::RegisterSpec for DOUT_MODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dout_mode::R]
(R) reader structure"]
impl crate::Readable for DOUT_MODE_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dout_mode::W]
(W) writer structure"]
impl crate::Writable for DOUT_MODE_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets DOUT_MODE to value 0"]
impl crate::Resettable for DOUT_MODE_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}