esp32 0.2.1

Peripheral access crate for the ESP32
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156

#[doc = "Reader of register CH4CONF0"]
pub type R = crate::R<u32, super::CH4CONF0>;
#[doc = "Writer for register CH4CONF0"]
pub type W = crate::W<u32, super::CH4CONF0>;
#[doc = "Register CH4CONF0 `reset()`'s with value 0"]
impl crate::ResetValue for super::CH4CONF0 {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "Reader of field `CARRIER_OUT_LV_CH4`"]
pub type CARRIER_OUT_LV_CH4_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CARRIER_OUT_LV_CH4`"]
pub struct CARRIER_OUT_LV_CH4_W<'a> {
    w: &'a mut W,
}
impl<'a> CARRIER_OUT_LV_CH4_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
        self.w
    }
}
#[doc = "Reader of field `CARRIER_EN_CH4`"]
pub type CARRIER_EN_CH4_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CARRIER_EN_CH4`"]
pub struct CARRIER_EN_CH4_W<'a> {
    w: &'a mut W,
}
impl<'a> CARRIER_EN_CH4_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
        self.w
    }
}
#[doc = "Reader of field `MEM_SIZE_CH4`"]
pub type MEM_SIZE_CH4_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `MEM_SIZE_CH4`"]
pub struct MEM_SIZE_CH4_W<'a> {
    w: &'a mut W,
}
impl<'a> MEM_SIZE_CH4_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
        self.w
    }
}
#[doc = "Reader of field `IDLE_THRES_CH4`"]
pub type IDLE_THRES_CH4_R = crate::R<u16, u16>;
#[doc = "Write proxy for field `IDLE_THRES_CH4`"]
pub struct IDLE_THRES_CH4_W<'a> {
    w: &'a mut W,
}
impl<'a> IDLE_THRES_CH4_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0xffff << 8)) | (((value as u32) & 0xffff) << 8);
        self.w
    }
}
#[doc = "Reader of field `DIV_CNT_CH4`"]
pub type DIV_CNT_CH4_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `DIV_CNT_CH4`"]
pub struct DIV_CNT_CH4_W<'a> {
    w: &'a mut W,
}
impl<'a> DIV_CNT_CH4_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
        self.w
    }
}
impl R {
    #[doc = "Bit 29"]
    #[inline(always)]
    pub fn carrier_out_lv_ch4(&self) -> CARRIER_OUT_LV_CH4_R {
        CARRIER_OUT_LV_CH4_R::new(((self.bits >> 29) & 0x01) != 0)
    }
    #[doc = "Bit 28"]
    #[inline(always)]
    pub fn carrier_en_ch4(&self) -> CARRIER_EN_CH4_R {
        CARRIER_EN_CH4_R::new(((self.bits >> 28) & 0x01) != 0)
    }
    #[doc = "Bits 24:27"]
    #[inline(always)]
    pub fn mem_size_ch4(&self) -> MEM_SIZE_CH4_R {
        MEM_SIZE_CH4_R::new(((self.bits >> 24) & 0x0f) as u8)
    }
    #[doc = "Bits 8:23"]
    #[inline(always)]
    pub fn idle_thres_ch4(&self) -> IDLE_THRES_CH4_R {
        IDLE_THRES_CH4_R::new(((self.bits >> 8) & 0xffff) as u16)
    }
    #[doc = "Bits 0:7"]
    #[inline(always)]
    pub fn div_cnt_ch4(&self) -> DIV_CNT_CH4_R {
        DIV_CNT_CH4_R::new((self.bits & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bit 29"]
    #[inline(always)]
    pub fn carrier_out_lv_ch4(&mut self) -> CARRIER_OUT_LV_CH4_W {
        CARRIER_OUT_LV_CH4_W { w: self }
    }
    #[doc = "Bit 28"]
    #[inline(always)]
    pub fn carrier_en_ch4(&mut self) -> CARRIER_EN_CH4_W {
        CARRIER_EN_CH4_W { w: self }
    }
    #[doc = "Bits 24:27"]
    #[inline(always)]
    pub fn mem_size_ch4(&mut self) -> MEM_SIZE_CH4_W {
        MEM_SIZE_CH4_W { w: self }
    }
    #[doc = "Bits 8:23"]
    #[inline(always)]
    pub fn idle_thres_ch4(&mut self) -> IDLE_THRES_CH4_W {
        IDLE_THRES_CH4_W { w: self }
    }
    #[doc = "Bits 0:7"]
    #[inline(always)]
    pub fn div_cnt_ch4(&mut self) -> DIV_CNT_CH4_W {
        DIV_CNT_CH4_W { w: self }
    }
}