Struct esp32_hal::peripherals::MCPWM0

pub struct MCPWM0 { /* private fields */ }

Implementations

impl MCPWM0

pub unsafe fn steal() -> MCPWM0

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <MCPWM0 as Deref>::Target = {0x3ff5e000 as *const <esp32::MCPWM0 as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <MCPWM0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn clk_cfg(&self) -> &Reg<CLK_CFG_SPEC>

0x00 -

pub fn timer0_cfg0(&self) -> &Reg<TIMER0_CFG0_SPEC>

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pub fn timer0_cfg1(&self) -> &Reg<TIMER0_CFG1_SPEC>

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pub fn timer0_sync(&self) -> &Reg<TIMER0_SYNC_SPEC>

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pub fn timer0_status(&self) -> &Reg<TIMER0_STATUS_SPEC>

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pub fn timer1_cfg0(&self) -> &Reg<TIMER1_CFG0_SPEC>

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pub fn timer1_cfg1(&self) -> &Reg<TIMER1_CFG1_SPEC>

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pub fn timer1_sync(&self) -> &Reg<TIMER1_SYNC_SPEC>

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pub fn timer1_status(&self) -> &Reg<TIMER1_STATUS_SPEC>

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pub fn timer2_cfg0(&self) -> &Reg<TIMER2_CFG0_SPEC>

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pub fn timer2_cfg1(&self) -> &Reg<TIMER2_CFG1_SPEC>

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pub fn timer2_sync(&self) -> &Reg<TIMER2_SYNC_SPEC>

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pub fn timer2_status(&self) -> &Reg<TIMER2_STATUS_SPEC>

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pub fn timer_synci_cfg(&self) -> &Reg<TIMER_SYNCI_CFG_SPEC>

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pub fn operator_timersel(&self) -> &Reg<OPERATOR_TIMERSEL_SPEC>

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pub fn gen0_stmp_cfg(&self) -> &Reg<GEN0_STMP_CFG_SPEC>

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pub fn gen0_tstmp_a(&self) -> &Reg<GEN0_TSTMP_A_SPEC>

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pub fn gen0_tstmp_b(&self) -> &Reg<GEN0_TSTMP_B_SPEC>

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pub fn gen0_cfg0(&self) -> &Reg<GEN0_CFG0_SPEC>

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pub fn gen0_force(&self) -> &Reg<GEN0_FORCE_SPEC>

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pub fn gen0_a(&self) -> &Reg<GEN0_A_SPEC>

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pub fn gen0_b(&self) -> &Reg<GEN0_B_SPEC>

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pub fn dt0_cfg(&self) -> &Reg<DT0_CFG_SPEC>

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pub fn dt0_fed_cfg(&self) -> &Reg<DT0_FED_CFG_SPEC>

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pub fn dt0_red_cfg(&self) -> &Reg<DT0_RED_CFG_SPEC>

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pub fn carrier0_cfg(&self) -> &Reg<CARRIER0_CFG_SPEC>

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pub fn fh0_cfg0(&self) -> &Reg<FH0_CFG0_SPEC>

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pub fn fh0_cfg1(&self) -> &Reg<FH0_CFG1_SPEC>

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pub fn fh0_status(&self) -> &Reg<FH0_STATUS_SPEC>

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pub fn gen1_stmp_cfg(&self) -> &Reg<GEN1_STMP_CFG_SPEC>

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pub fn gen1_tstmp_a(&self) -> &Reg<GEN1_TSTMP_A_SPEC>

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pub fn gen1_tstmp_b(&self) -> &Reg<GEN1_TSTMP_B_SPEC>

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pub fn gen1_cfg0(&self) -> &Reg<GEN1_CFG0_SPEC>

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pub fn gen1_force(&self) -> &Reg<GEN1_FORCE_SPEC>

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pub fn gen1_a(&self) -> &Reg<GEN1_A_SPEC>

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pub fn gen1_b(&self) -> &Reg<GEN1_B_SPEC>

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pub fn dt1_cfg(&self) -> &Reg<DT1_CFG_SPEC>

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pub fn dt1_fed_cfg(&self) -> &Reg<DT1_FED_CFG_SPEC>

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pub fn dt1_red_cfg(&self) -> &Reg<DT1_RED_CFG_SPEC>

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pub fn carrier1_cfg(&self) -> &Reg<CARRIER1_CFG_SPEC>

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pub fn fh1_cfg0(&self) -> &Reg<FH1_CFG0_SPEC>

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pub fn fh1_cfg1(&self) -> &Reg<FH1_CFG1_SPEC>

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pub fn fh1_status(&self) -> &Reg<FH1_STATUS_SPEC>

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pub fn gen2_stmp_cfg(&self) -> &Reg<GEN2_STMP_CFG_SPEC>

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pub fn gen2_tstmp_a(&self) -> &Reg<GEN2_TSTMP_A_SPEC>

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pub fn gen2_tstmp_b(&self) -> &Reg<GEN2_TSTMP_B_SPEC>

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pub fn gen2_cfg0(&self) -> &Reg<GEN2_CFG0_SPEC>

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pub fn gen2_force(&self) -> &Reg<GEN2_FORCE_SPEC>

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pub fn gen2_a(&self) -> &Reg<GEN2_A_SPEC>

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pub fn gen2_b(&self) -> &Reg<GEN2_B_SPEC>

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pub fn dt2_cfg(&self) -> &Reg<DT2_CFG_SPEC>

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pub fn dt2_fed_cfg(&self) -> &Reg<DT2_FED_CFG_SPEC>

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pub fn dt2_red_cfg(&self) -> &Reg<DT2_RED_CFG_SPEC>

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pub fn carrier2_cfg(&self) -> &Reg<CARRIER2_CFG_SPEC>

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pub fn fh2_cfg0(&self) -> &Reg<FH2_CFG0_SPEC>

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pub fn fh2_cfg1(&self) -> &Reg<FH2_CFG1_SPEC>

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pub fn fh2_status(&self) -> &Reg<FH2_STATUS_SPEC>

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pub fn fault_detect(&self) -> &Reg<FAULT_DETECT_SPEC>

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pub fn cap_timer_cfg(&self) -> &Reg<CAP_TIMER_CFG_SPEC>

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pub fn cap_timer_phase(&self) -> &Reg<CAP_TIMER_PHASE_SPEC>

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pub fn cap_ch0_cfg(&self) -> &Reg<CAP_CH0_CFG_SPEC>

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pub fn cap_ch1_cfg(&self) -> &Reg<CAP_CH1_CFG_SPEC>

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pub fn cap_ch2_cfg(&self) -> &Reg<CAP_CH2_CFG_SPEC>

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pub fn cap_ch0(&self) -> &Reg<CAP_CH0_SPEC>

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pub fn cap_ch1(&self) -> &Reg<CAP_CH1_SPEC>

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pub fn cap_ch2(&self) -> &Reg<CAP_CH2_SPEC>

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pub fn cap_status(&self) -> &Reg<CAP_STATUS_SPEC>

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pub fn update_cfg(&self) -> &Reg<UPDATE_CFG_SPEC>

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pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

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pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

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pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

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pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

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pub fn clk(&self) -> &Reg<CLK_SPEC>

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pub fn version(&self) -> &Reg<VERSION_SPEC>

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Trait Implementations

impl Debug for MCPWM0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for MCPWM0

type Target = <MCPWM0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<MCPWM0 as Deref>::Target

Dereferences the value.

impl DerefMut for MCPWM0

fn deref_mut(&mut self) -> &mut <MCPWM0 as Deref>::Target

Mutably dereferences the value.

impl Peripheral for MCPWM0

type P = MCPWM0

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <MCPWM0 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.

impl PwmPeripheral for MCPWM0

fn enable()

Enable peripheral

fn block() -> *const RegisterBlock

Get a pointer to the peripheral RegisterBlock

fn output_signal<const OP: u8, const IS_A: bool>() -> OutputSignal

Get operator GPIO mux output signal