esp-metadata-generated 0.4.0

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo xtask update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32c3"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32-C3"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32c3"
    };
    ("arch") => {
        "riscv"
    };
    ("cores") => {
        1
    };
    ("cores", str) => {
        stringify!(1)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf"
    };
    ("aes.dma") => {
        true
    };
    ("aes.has_split_text_registers") => {
        true
    };
    ("aes.endianness_configurable") => {
        false
    };
    ("assist_debug.has_sp_monitor") => {
        true
    };
    ("assist_debug.has_region_monitor") => {
        true
    };
    ("bt.controller") => {
        "btdm"
    };
    ("dedicated_gpio.needs_initialization") => {
        false
    };
    ("dedicated_gpio.channel_count") => {
        8
    };
    ("dedicated_gpio.channel_count", str) => {
        stringify!(8)
    };
    ("dma.kind") => {
        "gdma"
    };
    ("dma.supports_mem2mem") => {
        true
    };
    ("dma.can_access_psram") => {
        false
    };
    ("dma.ext_mem_configurable_block_size") => {
        false
    };
    ("dma.separate_in_out_interrupts") => {
        false
    };
    ("dma.max_priority") => {
        9
    };
    ("dma.max_priority", str) => {
        stringify!(9)
    };
    ("dma.gdma_version") => {
        1
    };
    ("dma.gdma_version", str) => {
        stringify!(1)
    };
    ("gpio.has_bank_1") => {
        false
    };
    ("gpio.gpio_function") => {
        1
    };
    ("gpio.gpio_function", str) => {
        stringify!(1)
    };
    ("gpio.constant_0_input") => {
        31
    };
    ("gpio.constant_0_input", str) => {
        stringify!(31)
    };
    ("gpio.constant_1_input") => {
        30
    };
    ("gpio.constant_1_input", str) => {
        stringify!(30)
    };
    ("gpio.remap_iomux_pin_registers") => {
        false
    };
    ("gpio.func_in_sel_offset") => {
        0
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(0)
    };
    ("gpio.input_signal_max") => {
        100
    };
    ("gpio.input_signal_max", str) => {
        stringify!(100)
    };
    ("gpio.output_signal_max") => {
        128
    };
    ("gpio.output_signal_max", str) => {
        stringify!(128)
    };
    ("i2c_master.has_fsm_timeouts") => {
        true
    };
    ("i2c_master.has_hw_bus_clear") => {
        true
    };
    ("i2c_master.has_bus_timeout_enable") => {
        true
    };
    ("i2c_master.separate_filter_config_registers") => {
        false
    };
    ("i2c_master.can_estimate_nack_reason") => {
        false
    };
    ("i2c_master.has_conf_update") => {
        true
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        false
    };
    ("i2c_master.has_arbitration_en") => {
        true
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        true
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        true
    };
    ("i2c_master.max_bus_timeout") => {
        31
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(31)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        32
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(32)
    };
    ("interrupts.status_registers") => {
        2
    };
    ("interrupts.status_registers", str) => {
        stringify!(2)
    };
    ("interrupts.disabled_interrupt") => {
        0
    };
    ("phy.combo_module") => {
        true
    };
    ("phy.backed_up_digital_register_count") => {
        21
    };
    ("phy.backed_up_digital_register_count", str) => {
        stringify!(21)
    };
    ("rmt.ram_start") => {
        1610703872
    };
    ("rmt.ram_start", str) => {
        stringify!(1610703872)
    };
    ("rmt.channel_ram_size") => {
        48
    };
    ("rmt.channel_ram_size", str) => {
        stringify!(48)
    };
    ("rmt.has_tx_immediate_stop") => {
        true
    };
    ("rmt.has_tx_loop_count") => {
        true
    };
    ("rmt.has_tx_loop_auto_stop") => {
        false
    };
    ("rmt.has_tx_carrier_data_only") => {
        true
    };
    ("rmt.has_tx_sync") => {
        true
    };
    ("rmt.has_rx_wrap") => {
        true
    };
    ("rmt.has_rx_demodulation") => {
        true
    };
    ("rmt.has_dma") => {
        false
    };
    ("rmt.has_per_channel_clock") => {
        false
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rsa.size_increment") => {
        32
    };
    ("rsa.size_increment", str) => {
        stringify!(32)
    };
    ("rsa.memory_size_bytes") => {
        384
    };
    ("rsa.memory_size_bytes", str) => {
        stringify!(384)
    };
    ("sha.dma") => {
        true
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("soc.cpu_has_branch_predictor") => {
        false
    };
    ("soc.cpu_has_csr_pc") => {
        true
    };
    ("soc.multi_core_enabled") => {
        false
    };
    ("soc.rc_fast_clk_default") => {
        17500000
    };
    ("soc.rc_fast_clk_default", str) => {
        stringify!(17500000)
    };
    ("clock_tree.system_pre_div.divisor") => {
        (0, 1023)
    };
    ("clock_tree.rc_fast_clk_div_n.divisor") => {
        (0, 3)
    };
    ("clock_tree.uart.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 4095)
    };
    ("spi_master.supports_dma") => {
        true
    };
    ("spi_master.has_octal") => {
        false
    };
    ("spi_master.has_app_interrupts") => {
        true
    };
    ("spi_master.has_dma_segmented_transfer") => {
        true
    };
    ("spi_master.has_clk_pre_div") => {
        false
    };
    ("spi_slave.supports_dma") => {
        true
    };
    ("timergroup.timg_has_timer1") => {
        false
    };
    ("timergroup.timg_has_divcnt_rst") => {
        true
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.peripheral_controls_mem_clk") => {
        false
    };
    ("uart.has_sclk_divider") => {
        true
    };
    ("uhci.combined_uart_selector_field") => {
        false
    };
    ("wifi.has_wifi6") => {
        false
    };
    ("wifi.mac_version") => {
        1
    };
    ("wifi.mac_version", str) => {
        stringify!(1)
    };
    ("wifi.has_5g") => {
        false
    };
    ("wifi.csi_supported") => {
        true
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_aes_key_length {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_aes_key_length { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_aes_key_length!((128));
        _for_each_inner_aes_key_length!((256)); _for_each_inner_aes_key_length!((128, 0,
        4)); _for_each_inner_aes_key_length!((256, 2, 6));
        _for_each_inner_aes_key_length!((bits(128), (256)));
        _for_each_inner_aes_key_length!((modes(128, 0, 4), (256, 2, 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dedicated_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dedicated_gpio { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_dedicated_gpio!((0));
        _for_each_inner_dedicated_gpio!((1)); _for_each_inner_dedicated_gpio!((2));
        _for_each_inner_dedicated_gpio!((3)); _for_each_inner_dedicated_gpio!((4));
        _for_each_inner_dedicated_gpio!((5)); _for_each_inner_dedicated_gpio!((6));
        _for_each_inner_dedicated_gpio!((7)); _for_each_inner_dedicated_gpio!((0, 0,
        CPU_GPIO_0)); _for_each_inner_dedicated_gpio!((0, 1, CPU_GPIO_1));
        _for_each_inner_dedicated_gpio!((0, 2, CPU_GPIO_2));
        _for_each_inner_dedicated_gpio!((0, 3, CPU_GPIO_3));
        _for_each_inner_dedicated_gpio!((0, 4, CPU_GPIO_4));
        _for_each_inner_dedicated_gpio!((0, 5, CPU_GPIO_5));
        _for_each_inner_dedicated_gpio!((0, 6, CPU_GPIO_6));
        _for_each_inner_dedicated_gpio!((0, 7, CPU_GPIO_7));
        _for_each_inner_dedicated_gpio!((channels(0), (1), (2), (3), (4), (5), (6),
        (7))); _for_each_inner_dedicated_gpio!((signals(0, 0, CPU_GPIO_0), (0, 1,
        CPU_GPIO_1), (0, 2, CPU_GPIO_2), (0, 3, CPU_GPIO_3), (0, 4, CPU_GPIO_4), (0, 5,
        CPU_GPIO_5), (0, 6, CPU_GPIO_6), (0, 7, CPU_GPIO_7)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_interrupt!(([disabled 0] 0));
        _for_each_inner_interrupt!(([reserved 0] 1));
        _for_each_inner_interrupt!(([direct_bindable 0] 2));
        _for_each_inner_interrupt!(([direct_bindable 1] 3));
        _for_each_inner_interrupt!(([direct_bindable 2] 4));
        _for_each_inner_interrupt!(([direct_bindable 3] 5));
        _for_each_inner_interrupt!(([direct_bindable 4] 6));
        _for_each_inner_interrupt!(([direct_bindable 5] 7));
        _for_each_inner_interrupt!(([direct_bindable 6] 8));
        _for_each_inner_interrupt!(([direct_bindable 7] 9));
        _for_each_inner_interrupt!(([direct_bindable 8] 10));
        _for_each_inner_interrupt!(([direct_bindable 9] 11));
        _for_each_inner_interrupt!(([direct_bindable 10] 12));
        _for_each_inner_interrupt!(([direct_bindable 11] 13));
        _for_each_inner_interrupt!(([direct_bindable 12] 14));
        _for_each_inner_interrupt!(([direct_bindable 13] 15));
        _for_each_inner_interrupt!(([direct_bindable 14] 16));
        _for_each_inner_interrupt!(([vector 0] 17)); _for_each_inner_interrupt!(([vector
        1] 18)); _for_each_inner_interrupt!(([vector 2] 19));
        _for_each_inner_interrupt!(([vector 3] 20)); _for_each_inner_interrupt!(([vector
        4] 21)); _for_each_inner_interrupt!(([vector 5] 22));
        _for_each_inner_interrupt!(([vector 6] 23)); _for_each_inner_interrupt!(([vector
        7] 24)); _for_each_inner_interrupt!(([vector 8] 25));
        _for_each_inner_interrupt!(([vector 9] 26)); _for_each_inner_interrupt!(([vector
        10] 27)); _for_each_inner_interrupt!(([vector 11] 28));
        _for_each_inner_interrupt!(([vector 12] 29)); _for_each_inner_interrupt!(([vector
        13] 30)); _for_each_inner_interrupt!(([vector 14] 31));
        _for_each_inner_interrupt!((all([disabled 0] 0), ([reserved 0] 1),
        ([direct_bindable 0] 2), ([direct_bindable 1] 3), ([direct_bindable 2] 4),
        ([direct_bindable 3] 5), ([direct_bindable 4] 6), ([direct_bindable 5] 7),
        ([direct_bindable 6] 8), ([direct_bindable 7] 9), ([direct_bindable 8] 10),
        ([direct_bindable 9] 11), ([direct_bindable 10] 12), ([direct_bindable 11] 13),
        ([direct_bindable 12] 14), ([direct_bindable 13] 15), ([direct_bindable 14] 16),
        ([vector 0] 17), ([vector 1] 18), ([vector 2] 19), ([vector 3] 20), ([vector 4]
        21), ([vector 5] 22), ([vector 6] 23), ([vector 7] 24), ([vector 8] 25), ([vector
        9] 26), ([vector 10] 27), ([vector 11] 28), ([vector 12] 29), ([vector 13] 30),
        ([vector 14] 31)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_classified_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_classified_interrupt { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_classified_interrupt!(([direct_bindable 0]
        2)); _for_each_inner_classified_interrupt!(([direct_bindable 1] 3));
        _for_each_inner_classified_interrupt!(([direct_bindable 2] 4));
        _for_each_inner_classified_interrupt!(([direct_bindable 3] 5));
        _for_each_inner_classified_interrupt!(([direct_bindable 4] 6));
        _for_each_inner_classified_interrupt!(([direct_bindable 5] 7));
        _for_each_inner_classified_interrupt!(([direct_bindable 6] 8));
        _for_each_inner_classified_interrupt!(([direct_bindable 7] 9));
        _for_each_inner_classified_interrupt!(([direct_bindable 8] 10));
        _for_each_inner_classified_interrupt!(([direct_bindable 9] 11));
        _for_each_inner_classified_interrupt!(([direct_bindable 10] 12));
        _for_each_inner_classified_interrupt!(([direct_bindable 11] 13));
        _for_each_inner_classified_interrupt!(([direct_bindable 12] 14));
        _for_each_inner_classified_interrupt!(([direct_bindable 13] 15));
        _for_each_inner_classified_interrupt!(([direct_bindable 14] 16));
        _for_each_inner_classified_interrupt!(([vector 0] 17));
        _for_each_inner_classified_interrupt!(([vector 1] 18));
        _for_each_inner_classified_interrupt!(([vector 2] 19));
        _for_each_inner_classified_interrupt!(([vector 3] 20));
        _for_each_inner_classified_interrupt!(([vector 4] 21));
        _for_each_inner_classified_interrupt!(([vector 5] 22));
        _for_each_inner_classified_interrupt!(([vector 6] 23));
        _for_each_inner_classified_interrupt!(([vector 7] 24));
        _for_each_inner_classified_interrupt!(([vector 8] 25));
        _for_each_inner_classified_interrupt!(([vector 9] 26));
        _for_each_inner_classified_interrupt!(([vector 10] 27));
        _for_each_inner_classified_interrupt!(([vector 11] 28));
        _for_each_inner_classified_interrupt!(([vector 12] 29));
        _for_each_inner_classified_interrupt!(([vector 13] 30));
        _for_each_inner_classified_interrupt!(([vector 14] 31));
        _for_each_inner_classified_interrupt!(([reserved 0] 1));
        _for_each_inner_classified_interrupt!((direct_bindable([direct_bindable 0] 2),
        ([direct_bindable 1] 3), ([direct_bindable 2] 4), ([direct_bindable 3] 5),
        ([direct_bindable 4] 6), ([direct_bindable 5] 7), ([direct_bindable 6] 8),
        ([direct_bindable 7] 9), ([direct_bindable 8] 10), ([direct_bindable 9] 11),
        ([direct_bindable 10] 12), ([direct_bindable 11] 13), ([direct_bindable 12] 14),
        ([direct_bindable 13] 15), ([direct_bindable 14] 16)));
        _for_each_inner_classified_interrupt!((vector([vector 0] 17), ([vector 1] 18),
        ([vector 2] 19), ([vector 3] 20), ([vector 4] 21), ([vector 5] 22), ([vector 6]
        23), ([vector 7] 24), ([vector 8] 25), ([vector 9] 26), ([vector 10] 27),
        ([vector 11] 28), ([vector 12] 29), ([vector 13] 30), ([vector 14] 31)));
        _for_each_inner_classified_interrupt!((reserved([reserved 0] 1)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt_priority {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt_priority { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_interrupt_priority!((0, 1, Priority1,
        Level1)); _for_each_inner_interrupt_priority!((1, 2, Priority2, Level2));
        _for_each_inner_interrupt_priority!((2, 3, Priority3, Level3));
        _for_each_inner_interrupt_priority!((3, 4, Priority4, Level4));
        _for_each_inner_interrupt_priority!((4, 5, Priority5, Level5));
        _for_each_inner_interrupt_priority!((5, 6, Priority6, Level6));
        _for_each_inner_interrupt_priority!((6, 7, Priority7, Level7));
        _for_each_inner_interrupt_priority!((7, 8, Priority8, Level8));
        _for_each_inner_interrupt_priority!((8, 9, Priority9, Level9));
        _for_each_inner_interrupt_priority!((9, 10, Priority10, Level10));
        _for_each_inner_interrupt_priority!((10, 11, Priority11, Level11));
        _for_each_inner_interrupt_priority!((11, 12, Priority12, Level12));
        _for_each_inner_interrupt_priority!((12, 13, Priority13, Level13));
        _for_each_inner_interrupt_priority!((13, 14, Priority14, Level14));
        _for_each_inner_interrupt_priority!((14, 15, Priority15, Level15));
        _for_each_inner_interrupt_priority!((all(0, 1, Priority1, Level1), (1, 2,
        Priority2, Level2), (2, 3, Priority3, Level3), (3, 4, Priority4, Level4), (4, 5,
        Priority5, Level5), (5, 6, Priority6, Level6), (6, 7, Priority7, Level7), (7, 8,
        Priority8, Level8), (8, 9, Priority9, Level9), (9, 10, Priority10, Level10), (10,
        11, Priority11, Level11), (11, 12, Priority12, Level12), (12, 13, Priority13,
        Level13), (13, 14, Priority14, Level14), (14, 15, Priority15, Level15)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
macro_rules! sw_interrupt_delay {
    () => {
        unsafe {
            ::core::arch::asm!("nop");
            ::core::arch::asm!("nop");
            ::core::arch::asm!("nop");
            ::core::arch::asm!("nop");
            ::core::arch::asm!("nop");
        }
    };
}
/// This macro can be used to generate code for each channel of the RMT peripheral.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has three options for its "Individual matcher" case:
///
/// - `all`: `($num:literal)`
/// - `tx`: `($num:literal, $idx:literal)`
/// - `rx`: `($num:literal, $idx:literal)`
///
/// Macro fragments:
///
/// - `$num`: number of the channel, e.g. `0`
/// - `$idx`: index of the channel among channels of the same capability, e.g. `0`
///
/// Example data:
///
/// - `all`: `(0)`
/// - `tx`: `(1, 1)`
/// - `rx`: `(2, 0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rmt_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rmt_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_rmt_channel!((0)); _for_each_inner_rmt_channel!((1));
        _for_each_inner_rmt_channel!((2)); _for_each_inner_rmt_channel!((3));
        _for_each_inner_rmt_channel!((0, 0)); _for_each_inner_rmt_channel!((1, 1));
        _for_each_inner_rmt_channel!((2, 0)); _for_each_inner_rmt_channel!((3, 1));
        _for_each_inner_rmt_channel!((all(0), (1), (2), (3)));
        _for_each_inner_rmt_channel!((tx(0, 0), (1, 1)));
        _for_each_inner_rmt_channel!((rx(2, 0), (3, 1)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rmt_clock_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rmt_clock_source { $(($pattern) => $code;)* ($other
        : tt) => {} } _for_each_inner_rmt_clock_source!((Apb, 1));
        _for_each_inner_rmt_clock_source!((RcFast, 2));
        _for_each_inner_rmt_clock_source!((Xtal, 3));
        _for_each_inner_rmt_clock_source!((Apb));
        _for_each_inner_rmt_clock_source!((all(Apb, 1), (RcFast, 2), (Xtal, 3)));
        _for_each_inner_rmt_clock_source!((default(Apb)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_exponentiation {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_exponentiation { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_exponentiation!((32));
        _for_each_inner_rsa_exponentiation!((64));
        _for_each_inner_rsa_exponentiation!((96));
        _for_each_inner_rsa_exponentiation!((128));
        _for_each_inner_rsa_exponentiation!((160));
        _for_each_inner_rsa_exponentiation!((192));
        _for_each_inner_rsa_exponentiation!((224));
        _for_each_inner_rsa_exponentiation!((256));
        _for_each_inner_rsa_exponentiation!((288));
        _for_each_inner_rsa_exponentiation!((320));
        _for_each_inner_rsa_exponentiation!((352));
        _for_each_inner_rsa_exponentiation!((384));
        _for_each_inner_rsa_exponentiation!((416));
        _for_each_inner_rsa_exponentiation!((448));
        _for_each_inner_rsa_exponentiation!((480));
        _for_each_inner_rsa_exponentiation!((512));
        _for_each_inner_rsa_exponentiation!((544));
        _for_each_inner_rsa_exponentiation!((576));
        _for_each_inner_rsa_exponentiation!((608));
        _for_each_inner_rsa_exponentiation!((640));
        _for_each_inner_rsa_exponentiation!((672));
        _for_each_inner_rsa_exponentiation!((704));
        _for_each_inner_rsa_exponentiation!((736));
        _for_each_inner_rsa_exponentiation!((768));
        _for_each_inner_rsa_exponentiation!((800));
        _for_each_inner_rsa_exponentiation!((832));
        _for_each_inner_rsa_exponentiation!((864));
        _for_each_inner_rsa_exponentiation!((896));
        _for_each_inner_rsa_exponentiation!((928));
        _for_each_inner_rsa_exponentiation!((960));
        _for_each_inner_rsa_exponentiation!((992));
        _for_each_inner_rsa_exponentiation!((1024));
        _for_each_inner_rsa_exponentiation!((1056));
        _for_each_inner_rsa_exponentiation!((1088));
        _for_each_inner_rsa_exponentiation!((1120));
        _for_each_inner_rsa_exponentiation!((1152));
        _for_each_inner_rsa_exponentiation!((1184));
        _for_each_inner_rsa_exponentiation!((1216));
        _for_each_inner_rsa_exponentiation!((1248));
        _for_each_inner_rsa_exponentiation!((1280));
        _for_each_inner_rsa_exponentiation!((1312));
        _for_each_inner_rsa_exponentiation!((1344));
        _for_each_inner_rsa_exponentiation!((1376));
        _for_each_inner_rsa_exponentiation!((1408));
        _for_each_inner_rsa_exponentiation!((1440));
        _for_each_inner_rsa_exponentiation!((1472));
        _for_each_inner_rsa_exponentiation!((1504));
        _for_each_inner_rsa_exponentiation!((1536));
        _for_each_inner_rsa_exponentiation!((1568));
        _for_each_inner_rsa_exponentiation!((1600));
        _for_each_inner_rsa_exponentiation!((1632));
        _for_each_inner_rsa_exponentiation!((1664));
        _for_each_inner_rsa_exponentiation!((1696));
        _for_each_inner_rsa_exponentiation!((1728));
        _for_each_inner_rsa_exponentiation!((1760));
        _for_each_inner_rsa_exponentiation!((1792));
        _for_each_inner_rsa_exponentiation!((1824));
        _for_each_inner_rsa_exponentiation!((1856));
        _for_each_inner_rsa_exponentiation!((1888));
        _for_each_inner_rsa_exponentiation!((1920));
        _for_each_inner_rsa_exponentiation!((1952));
        _for_each_inner_rsa_exponentiation!((1984));
        _for_each_inner_rsa_exponentiation!((2016));
        _for_each_inner_rsa_exponentiation!((2048));
        _for_each_inner_rsa_exponentiation!((2080));
        _for_each_inner_rsa_exponentiation!((2112));
        _for_each_inner_rsa_exponentiation!((2144));
        _for_each_inner_rsa_exponentiation!((2176));
        _for_each_inner_rsa_exponentiation!((2208));
        _for_each_inner_rsa_exponentiation!((2240));
        _for_each_inner_rsa_exponentiation!((2272));
        _for_each_inner_rsa_exponentiation!((2304));
        _for_each_inner_rsa_exponentiation!((2336));
        _for_each_inner_rsa_exponentiation!((2368));
        _for_each_inner_rsa_exponentiation!((2400));
        _for_each_inner_rsa_exponentiation!((2432));
        _for_each_inner_rsa_exponentiation!((2464));
        _for_each_inner_rsa_exponentiation!((2496));
        _for_each_inner_rsa_exponentiation!((2528));
        _for_each_inner_rsa_exponentiation!((2560));
        _for_each_inner_rsa_exponentiation!((2592));
        _for_each_inner_rsa_exponentiation!((2624));
        _for_each_inner_rsa_exponentiation!((2656));
        _for_each_inner_rsa_exponentiation!((2688));
        _for_each_inner_rsa_exponentiation!((2720));
        _for_each_inner_rsa_exponentiation!((2752));
        _for_each_inner_rsa_exponentiation!((2784));
        _for_each_inner_rsa_exponentiation!((2816));
        _for_each_inner_rsa_exponentiation!((2848));
        _for_each_inner_rsa_exponentiation!((2880));
        _for_each_inner_rsa_exponentiation!((2912));
        _for_each_inner_rsa_exponentiation!((2944));
        _for_each_inner_rsa_exponentiation!((2976));
        _for_each_inner_rsa_exponentiation!((3008));
        _for_each_inner_rsa_exponentiation!((3040));
        _for_each_inner_rsa_exponentiation!((3072));
        _for_each_inner_rsa_exponentiation!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536),
        (1568), (1600), (1632), (1664), (1696), (1728), (1760), (1792), (1824), (1856),
        (1888), (1920), (1952), (1984), (2016), (2048), (2080), (2112), (2144), (2176),
        (2208), (2240), (2272), (2304), (2336), (2368), (2400), (2432), (2464), (2496),
        (2528), (2560), (2592), (2624), (2656), (2688), (2720), (2752), (2784), (2816),
        (2848), (2880), (2912), (2944), (2976), (3008), (3040), (3072)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_multiplication {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_multiplication { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_multiplication!((32));
        _for_each_inner_rsa_multiplication!((64));
        _for_each_inner_rsa_multiplication!((96));
        _for_each_inner_rsa_multiplication!((128));
        _for_each_inner_rsa_multiplication!((160));
        _for_each_inner_rsa_multiplication!((192));
        _for_each_inner_rsa_multiplication!((224));
        _for_each_inner_rsa_multiplication!((256));
        _for_each_inner_rsa_multiplication!((288));
        _for_each_inner_rsa_multiplication!((320));
        _for_each_inner_rsa_multiplication!((352));
        _for_each_inner_rsa_multiplication!((384));
        _for_each_inner_rsa_multiplication!((416));
        _for_each_inner_rsa_multiplication!((448));
        _for_each_inner_rsa_multiplication!((480));
        _for_each_inner_rsa_multiplication!((512));
        _for_each_inner_rsa_multiplication!((544));
        _for_each_inner_rsa_multiplication!((576));
        _for_each_inner_rsa_multiplication!((608));
        _for_each_inner_rsa_multiplication!((640));
        _for_each_inner_rsa_multiplication!((672));
        _for_each_inner_rsa_multiplication!((704));
        _for_each_inner_rsa_multiplication!((736));
        _for_each_inner_rsa_multiplication!((768));
        _for_each_inner_rsa_multiplication!((800));
        _for_each_inner_rsa_multiplication!((832));
        _for_each_inner_rsa_multiplication!((864));
        _for_each_inner_rsa_multiplication!((896));
        _for_each_inner_rsa_multiplication!((928));
        _for_each_inner_rsa_multiplication!((960));
        _for_each_inner_rsa_multiplication!((992));
        _for_each_inner_rsa_multiplication!((1024));
        _for_each_inner_rsa_multiplication!((1056));
        _for_each_inner_rsa_multiplication!((1088));
        _for_each_inner_rsa_multiplication!((1120));
        _for_each_inner_rsa_multiplication!((1152));
        _for_each_inner_rsa_multiplication!((1184));
        _for_each_inner_rsa_multiplication!((1216));
        _for_each_inner_rsa_multiplication!((1248));
        _for_each_inner_rsa_multiplication!((1280));
        _for_each_inner_rsa_multiplication!((1312));
        _for_each_inner_rsa_multiplication!((1344));
        _for_each_inner_rsa_multiplication!((1376));
        _for_each_inner_rsa_multiplication!((1408));
        _for_each_inner_rsa_multiplication!((1440));
        _for_each_inner_rsa_multiplication!((1472));
        _for_each_inner_rsa_multiplication!((1504));
        _for_each_inner_rsa_multiplication!((1536));
        _for_each_inner_rsa_multiplication!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha224, "SHA-224"(sizes : 64, 28, 8)
        (insecure_against : "length extension"), 1));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 2));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha224,
        "SHA-224"(sizes : 64, 28, 8) (insecure_against : "length extension"), 1),
        (Sha256, "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"),
        2)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// fn configure_xtal_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<XtalClkConfig>,
///     _new_config: XtalClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_CLK
///
/// fn enable_pll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_pll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<PllClkConfig>,
///     _new_config: PllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL32K_CLK
///
/// fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_DIV_CLK
///
/// fn enable_rc_fast_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV_IN
///
/// fn enable_system_pre_div_in_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_in_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivInConfig>,
///     _new_config: SystemPreDivInConfig,
/// ) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV
///
/// fn enable_system_pre_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivConfig>,
///     _new_config: SystemPreDivConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_PLL_DIV_OUT
///
/// fn enable_cpu_pll_div_out_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_pll_div_out_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuPllDivOutConfig>,
///     _new_config: CpuPllDivOutConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CRYPTO_CLK
///
/// fn enable_crypto_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_crypto_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CryptoClkConfig>,
///     _new_config: CryptoClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_80M
///
/// fn enable_pll_80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_160M
///
/// fn enable_pll_160m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_CLK_DIV_N
///
/// fn enable_rc_fast_clk_div_n_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rc_fast_clk_div_n_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RcFastClkDivNConfig>,
///     _new_config: RcFastClkDivNConfig,
/// ) {
///     todo!()
/// }
///
/// // XTAL_DIV_CLK
///
/// fn enable_xtal_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RTC_SLOW_CLK
///
/// fn enable_rtc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcSlowClkConfig>,
///     _new_config: RtcSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RTC_FAST_CLK
///
/// fn enable_rtc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcFastClkConfig>,
///     _new_config: RtcFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LOW_POWER_CLK
///
/// fn enable_low_power_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_low_power_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LowPowerClkConfig>,
///     _new_config: LowPowerClkConfig,
/// ) {
///     todo!()
/// }
///
/// // UART_MEM_CLK
///
/// fn enable_uart_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl RmtInstance {
///     // RMT_SCLK
///
///     fn enable_sclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_sclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<RmtSclkConfig>,
///         _new_config: RmtSclkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl TimgInstance {
///     // TIMG_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgFunctionClockConfig>,
///         _new_config: TimgFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // TIMG_WDT_CLOCK
///
///     fn enable_wdt_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_wdt_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgWdtClockConfig>,
///         _new_config: TimgWdtClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_MEM_CLOCK
///
///     fn enable_mem_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_mem_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartMemClockConfig>,
///         _new_config: UartMemClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtInstance {
            Rmt = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgInstance {
            Timg0 = 0,
            Timg1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
        }
        /// Selects the output frequency of `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum XtalClkConfig {
            /// 40 MHz
            _40,
        }
        impl XtalClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    XtalClkConfig::_40 => 40000000,
                }
            }
        }
        /// Selects the output frequency of `PLL_CLK`. Depends on `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum PllClkConfig {
            /// 320 MHz
            _320,
            /// 480 MHz
            _480,
        }
        impl PllClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    PllClkConfig::_320 => 320000000,
                    PllClkConfig::_480 => 480000000,
                }
            }
        }
        /// The list of clock signals that the `SYSTEM_PRE_DIV_IN` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SystemPreDivInConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `SYSTEM_PRE_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = SYSTEM_PRE_DIV_IN / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct SystemPreDivConfig {
            divisor: u32,
        }
        impl SystemPreDivConfig {
            /// Creates a new configuration for the SYSTEM_PRE_DIV clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 1023).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 1023,
                    "`SYSTEM_PRE_DIV` divisor must be between 0 and 1023 (inclusive)."
                );
                Self { divisor }
            }
            fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Selects the output frequency of `CPU_PLL_DIV_OUT`. Depends on `PLL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuPllDivOutConfig {
            /// 80 MHz
            _80,
            /// 160 MHz
            _160,
        }
        impl CpuPllDivOutConfig {
            pub fn value(&self) -> u32 {
                match self {
                    CpuPllDivOutConfig::_80 => 80000000,
                    CpuPllDivOutConfig::_160 => 160000000,
                }
            }
        }
        /// The list of clock signals that the `APB_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ApbClkConfig {
            /// Selects `PLL_80M`.
            Pll80m,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CRYPTO_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CryptoClkConfig {
            /// Selects `PLL_160M`.
            Pll160m,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CPU_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuClkConfig {
            /// Selects `SYSTEM_PRE_DIV`.
            Xtal,
            /// Selects `SYSTEM_PRE_DIV`.
            RcFast,
            /// Selects `CPU_PLL_DIV_OUT`.
            Pll,
        }
        /// Configures the `RC_FAST_CLK_DIV_N` clock node.
        ///
        /// The output is calculated as `OUTPUT = RC_FAST_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RcFastClkDivNConfig {
            divisor: u32,
        }
        impl RcFastClkDivNConfig {
            /// Creates a new configuration for the RC_FAST_CLK_DIV_N clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 3).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 3,
                    "`RC_FAST_CLK_DIV_N` divisor must be between 0 and 3 (inclusive)."
                );
                Self { divisor }
            }
            fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `RTC_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcSlowClkConfig {
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFast,
        }
        /// The list of clock signals that the `RTC_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcFastClkConfig {
            /// Selects `XTAL_DIV_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK_DIV_N`.
            Rc,
        }
        /// The list of clock signals that the `LOW_POWER_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LowPowerClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `RTC_SLOW_CLK`.
            RtcSlow,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlowClk,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFastDivClk,
            /// Selects `XTAL32K_CLK`.
            Xtal32kClk,
        }
        /// The list of clock signals that the `RMT_SCLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtSclkConfig {
            #[default]
            /// Selects `APB_CLK`.
            ApbClk,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `XTAL_CLK`.
            XtalClk,
        }
        /// The list of clock signals that the `TIMG0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `APB_CLK`.
            ApbClk,
        }
        /// The list of clock signals that the `TIMG0_WDT_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgWdtClockConfig {
            #[default]
            /// Selects `APB_CLK`.
            ApbClk,
            /// Selects `XTAL_CLK`.
            XtalClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            /// Selects `APB_CLK`.
            Apb,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
            div_num: u32,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: UartFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`UART0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
            fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// Configures the `UART0_MEM_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = UART_MEM_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartMemClockConfig {}
        impl UartMemClockConfig {
            /// Creates a new configuration for the MEM_CLOCK clock node.
            pub const fn new() -> Self {
                Self {}
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 4095).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 4095,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 4095 (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            fn fractional(self) -> u32 {
                self.fractional as u32
            }
            fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            xtal_clk: Option<XtalClkConfig>,
            pll_clk: Option<PllClkConfig>,
            system_pre_div_in: Option<SystemPreDivInConfig>,
            system_pre_div: Option<SystemPreDivConfig>,
            cpu_pll_div_out: Option<CpuPllDivOutConfig>,
            apb_clk: Option<ApbClkConfig>,
            crypto_clk: Option<CryptoClkConfig>,
            cpu_clk: Option<CpuClkConfig>,
            rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            rtc_slow_clk: Option<RtcSlowClkConfig>,
            rtc_fast_clk: Option<RtcFastClkConfig>,
            low_power_clk: Option<LowPowerClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            rmt_sclk: [Option<RmtSclkConfig>; 1],
            timg_function_clock: [Option<TimgFunctionClockConfig>; 2],
            timg_wdt_clock: [Option<TimgWdtClockConfig>; 2],
            uart_function_clock: [Option<UartFunctionClockConfig>; 2],
            uart_mem_clock: [Option<UartMemClockConfig>; 2],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 2],
            rc_fast_clk_refcount: u32,
            xtal32k_clk_refcount: u32,
            rc_slow_clk_refcount: u32,
            rc_fast_div_clk_refcount: u32,
            apb_clk_refcount: u32,
            crypto_clk_refcount: u32,
            rtc_fast_clk_refcount: u32,
            low_power_clk_refcount: u32,
            uart_mem_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            rmt_sclk_refcount: [u32; 1],
            timg_function_clock_refcount: [u32; 2],
            timg_wdt_clock_refcount: [u32; 2],
            uart_function_clock_refcount: [u32; 2],
            uart_mem_clock_refcount: [u32; 2],
            uart_baud_rate_generator_refcount: [u32; 2],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the XTAL_CLK clock tree node
            pub fn xtal_clk(&self) -> Option<XtalClkConfig> {
                self.xtal_clk
            }
            /// Returns the current configuration of the PLL_CLK clock tree node
            pub fn pll_clk(&self) -> Option<PllClkConfig> {
                self.pll_clk
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV_IN clock tree node
            pub fn system_pre_div_in(&self) -> Option<SystemPreDivInConfig> {
                self.system_pre_div_in
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV clock tree node
            pub fn system_pre_div(&self) -> Option<SystemPreDivConfig> {
                self.system_pre_div
            }
            /// Returns the current configuration of the CPU_PLL_DIV_OUT clock tree node
            pub fn cpu_pll_div_out(&self) -> Option<CpuPllDivOutConfig> {
                self.cpu_pll_div_out
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the CRYPTO_CLK clock tree node
            pub fn crypto_clk(&self) -> Option<CryptoClkConfig> {
                self.crypto_clk
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the RC_FAST_CLK_DIV_N clock tree node
            pub fn rc_fast_clk_div_n(&self) -> Option<RcFastClkDivNConfig> {
                self.rc_fast_clk_div_n
            }
            /// Returns the current configuration of the RTC_SLOW_CLK clock tree node
            pub fn rtc_slow_clk(&self) -> Option<RtcSlowClkConfig> {
                self.rtc_slow_clk
            }
            /// Returns the current configuration of the RTC_FAST_CLK clock tree node
            pub fn rtc_fast_clk(&self) -> Option<RtcFastClkConfig> {
                self.rtc_fast_clk
            }
            /// Returns the current configuration of the LOW_POWER_CLK clock tree node
            pub fn low_power_clk(&self) -> Option<LowPowerClkConfig> {
                self.low_power_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the RMT_SCLK clock tree node
            pub fn rmt_sclk(&self) -> Option<RmtSclkConfig> {
                self.rmt_sclk[RmtInstance::Rmt as usize]
            }
            /// Returns the current configuration of the TIMG0_FUNCTION_CLOCK clock tree node
            pub fn timg0_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG0_WDT_CLOCK clock tree node
            pub fn timg0_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG1_FUNCTION_CLOCK clock tree node
            pub fn timg1_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the TIMG1_WDT_CLOCK clock tree node
            pub fn timg1_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_MEM_CLOCK clock tree node
            pub fn uart0_mem_clock(&self) -> Option<UartMemClockConfig> {
                self.uart_mem_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_MEM_CLOCK clock tree node
            pub fn uart1_mem_clock(&self) -> Option<UartMemClockConfig> {
                self.uart_mem_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                xtal_clk: None,
                pll_clk: None,
                system_pre_div_in: None,
                system_pre_div: None,
                cpu_pll_div_out: None,
                apb_clk: None,
                crypto_clk: None,
                cpu_clk: None,
                rc_fast_clk_div_n: None,
                rtc_slow_clk: None,
                rtc_fast_clk: None,
                low_power_clk: None,
                timg_calibration_clock: None,
                rmt_sclk: [None; 1],
                timg_function_clock: [None; 2],
                timg_wdt_clock: [None; 2],
                uart_function_clock: [None; 2],
                uart_mem_clock: [None; 2],
                uart_baud_rate_generator: [None; 2],
                rc_fast_clk_refcount: 0,
                xtal32k_clk_refcount: 0,
                rc_slow_clk_refcount: 0,
                rc_fast_div_clk_refcount: 0,
                apb_clk_refcount: 0,
                crypto_clk_refcount: 0,
                rtc_fast_clk_refcount: 0,
                low_power_clk_refcount: 0,
                uart_mem_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                rmt_sclk_refcount: [0; 1],
                timg_function_clock_refcount: [0; 2],
                timg_wdt_clock_refcount: [0; 2],
                uart_function_clock_refcount: [0; 2],
                uart_mem_clock_refcount: [0; 2],
                uart_baud_rate_generator_refcount: [0; 2],
            });
        pub fn configure_xtal_clk(clocks: &mut ClockTree, config: XtalClkConfig) {
            let old_config = clocks.xtal_clk.replace(config);
            configure_xtal_clk_impl(clocks, old_config, config);
        }
        pub fn xtal_clk_config(clocks: &mut ClockTree) -> Option<XtalClkConfig> {
            clocks.xtal_clk
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        #[allow(unused_variables)]
        pub fn xtal_clk_config_frequency(clocks: &mut ClockTree, config: XtalClkConfig) -> u32 {
            config.value()
        }
        pub fn xtal_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.xtal_clk {
                xtal_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_pll_clk(clocks: &mut ClockTree, config: PllClkConfig) {
            let old_config = clocks.pll_clk.replace(config);
            configure_pll_clk_impl(clocks, old_config, config);
        }
        pub fn pll_clk_config(clocks: &mut ClockTree) -> Option<PllClkConfig> {
            clocks.pll_clk
        }
        pub fn request_pll_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_CLK");
            trace!("Enabling PLL_CLK");
            request_xtal_clk(clocks);
            enable_pll_clk_impl(clocks, true);
        }
        pub fn release_pll_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_CLK");
            trace!("Disabling PLL_CLK");
            enable_pll_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        #[allow(unused_variables)]
        pub fn pll_clk_config_frequency(clocks: &mut ClockTree, config: PllClkConfig) -> u32 {
            config.value()
        }
        pub fn pll_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.pll_clk {
                pll_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        pub fn rc_fast_clk_frequency(clocks: &mut ClockTree) -> u32 {
            17500000
        }
        pub fn request_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL32K_CLK");
            if increment_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Enabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, true);
            }
        }
        pub fn release_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL32K_CLK");
            if decrement_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Disabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, false);
            }
        }
        pub fn xtal32k_clk_frequency(clocks: &mut ClockTree) -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Enabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Disabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, false);
            }
        }
        pub fn rc_slow_clk_frequency(clocks: &mut ClockTree) -> u32 {
            136000
        }
        pub fn request_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_DIV_CLK");
            if increment_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Enabling RC_FAST_DIV_CLK");
                request_rc_fast_clk(clocks);
                enable_rc_fast_div_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_DIV_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Disabling RC_FAST_DIV_CLK");
                enable_rc_fast_div_clk_impl(clocks, false);
                release_rc_fast_clk(clocks);
            }
        }
        pub fn rc_fast_div_clk_frequency(clocks: &mut ClockTree) -> u32 {
            (rc_fast_clk_frequency(clocks) / 256)
        }
        pub fn configure_system_pre_div_in(
            clocks: &mut ClockTree,
            new_selector: SystemPreDivInConfig,
        ) {
            let old_selector = clocks.system_pre_div_in.replace(new_selector);
            match new_selector {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            configure_system_pre_div_in_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                    SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn system_pre_div_in_config(clocks: &mut ClockTree) -> Option<SystemPreDivInConfig> {
            clocks.system_pre_div_in
        }
        pub fn request_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Requesting SYSTEM_PRE_DIV_IN");
            trace!("Enabling SYSTEM_PRE_DIV_IN");
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            enable_system_pre_div_in_impl(clocks, true);
        }
        pub fn release_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Releasing SYSTEM_PRE_DIV_IN");
            trace!("Disabling SYSTEM_PRE_DIV_IN");
            enable_system_pre_div_in_impl(clocks, false);
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
            }
        }
        #[allow(unused_variables)]
        pub fn system_pre_div_in_config_frequency(
            clocks: &mut ClockTree,
            config: SystemPreDivInConfig,
        ) -> u32 {
            match config {
                SystemPreDivInConfig::Xtal => xtal_clk_frequency(clocks),
                SystemPreDivInConfig::RcFast => rc_fast_clk_frequency(clocks),
            }
        }
        pub fn system_pre_div_in_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.system_pre_div_in {
                system_pre_div_in_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_system_pre_div(clocks: &mut ClockTree, config: SystemPreDivConfig) {
            let old_config = clocks.system_pre_div.replace(config);
            configure_system_pre_div_impl(clocks, old_config, config);
        }
        pub fn system_pre_div_config(clocks: &mut ClockTree) -> Option<SystemPreDivConfig> {
            clocks.system_pre_div
        }
        pub fn request_system_pre_div(clocks: &mut ClockTree) {
            trace!("Requesting SYSTEM_PRE_DIV");
            trace!("Enabling SYSTEM_PRE_DIV");
            request_system_pre_div_in(clocks);
            enable_system_pre_div_impl(clocks, true);
        }
        pub fn release_system_pre_div(clocks: &mut ClockTree) {
            trace!("Releasing SYSTEM_PRE_DIV");
            trace!("Disabling SYSTEM_PRE_DIV");
            enable_system_pre_div_impl(clocks, false);
            release_system_pre_div_in(clocks);
        }
        #[allow(unused_variables)]
        pub fn system_pre_div_config_frequency(
            clocks: &mut ClockTree,
            config: SystemPreDivConfig,
        ) -> u32 {
            (system_pre_div_in_frequency(clocks) / (config.divisor() + 1))
        }
        pub fn system_pre_div_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.system_pre_div {
                system_pre_div_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_cpu_pll_div_out(clocks: &mut ClockTree, config: CpuPllDivOutConfig) {
            let old_config = clocks.cpu_pll_div_out.replace(config);
            configure_cpu_pll_div_out_impl(clocks, old_config, config);
        }
        pub fn cpu_pll_div_out_config(clocks: &mut ClockTree) -> Option<CpuPllDivOutConfig> {
            clocks.cpu_pll_div_out
        }
        pub fn request_cpu_pll_div_out(clocks: &mut ClockTree) {
            trace!("Requesting CPU_PLL_DIV_OUT");
            trace!("Enabling CPU_PLL_DIV_OUT");
            request_pll_clk(clocks);
            enable_cpu_pll_div_out_impl(clocks, true);
        }
        pub fn release_cpu_pll_div_out(clocks: &mut ClockTree) {
            trace!("Releasing CPU_PLL_DIV_OUT");
            trace!("Disabling CPU_PLL_DIV_OUT");
            enable_cpu_pll_div_out_impl(clocks, false);
            release_pll_clk(clocks);
        }
        #[allow(unused_variables)]
        pub fn cpu_pll_div_out_config_frequency(
            clocks: &mut ClockTree,
            config: CpuPllDivOutConfig,
        ) -> u32 {
            config.value()
        }
        pub fn cpu_pll_div_out_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.cpu_pll_div_out {
                cpu_pll_div_out_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, new_selector: ApbClkConfig) {
            let old_selector = clocks.apb_clk.replace(new_selector);
            if clocks.apb_clk_refcount > 0 {
                match new_selector {
                    ApbClkConfig::Pll80m => request_pll_80m(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
                configure_apb_clk_impl(clocks, old_selector, new_selector);
                if let Some(old_selector) = old_selector {
                    match old_selector {
                        ApbClkConfig::Pll80m => release_pll_80m(clocks),
                        ApbClkConfig::Cpu => release_cpu_clk(clocks),
                    }
                }
            } else {
                configure_apb_clk_impl(clocks, old_selector, new_selector);
            }
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Requesting APB_CLK");
            if increment_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Enabling APB_CLK");
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll80m => request_pll_80m(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_apb_clk_impl(clocks, true);
            }
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Releasing APB_CLK");
            if decrement_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Disabling APB_CLK");
                enable_apb_clk_impl(clocks, false);
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll80m => release_pll_80m(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        #[allow(unused_variables)]
        pub fn apb_clk_config_frequency(clocks: &mut ClockTree, config: ApbClkConfig) -> u32 {
            match config {
                ApbClkConfig::Pll80m => pll_80m_frequency(clocks),
                ApbClkConfig::Cpu => cpu_clk_frequency(clocks),
            }
        }
        pub fn apb_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.apb_clk {
                apb_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_crypto_clk(clocks: &mut ClockTree, new_selector: CryptoClkConfig) {
            let old_selector = clocks.crypto_clk.replace(new_selector);
            if clocks.crypto_clk_refcount > 0 {
                match new_selector {
                    CryptoClkConfig::Pll160m => request_pll_160m(clocks),
                    CryptoClkConfig::Cpu => request_cpu_clk(clocks),
                }
                configure_crypto_clk_impl(clocks, old_selector, new_selector);
                if let Some(old_selector) = old_selector {
                    match old_selector {
                        CryptoClkConfig::Pll160m => release_pll_160m(clocks),
                        CryptoClkConfig::Cpu => release_cpu_clk(clocks),
                    }
                }
            } else {
                configure_crypto_clk_impl(clocks, old_selector, new_selector);
            }
        }
        pub fn crypto_clk_config(clocks: &mut ClockTree) -> Option<CryptoClkConfig> {
            clocks.crypto_clk
        }
        pub fn request_crypto_clk(clocks: &mut ClockTree) {
            trace!("Requesting CRYPTO_CLK");
            if increment_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Enabling CRYPTO_CLK");
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Pll160m => request_pll_160m(clocks),
                    CryptoClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_crypto_clk_impl(clocks, true);
            }
        }
        pub fn release_crypto_clk(clocks: &mut ClockTree) {
            trace!("Releasing CRYPTO_CLK");
            if decrement_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Disabling CRYPTO_CLK");
                enable_crypto_clk_impl(clocks, false);
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Pll160m => release_pll_160m(clocks),
                    CryptoClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        #[allow(unused_variables)]
        pub fn crypto_clk_config_frequency(clocks: &mut ClockTree, config: CryptoClkConfig) -> u32 {
            match config {
                CryptoClkConfig::Pll160m => pll_160m_frequency(clocks),
                CryptoClkConfig::Cpu => cpu_clk_frequency(clocks),
            }
        }
        pub fn crypto_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.crypto_clk {
                crypto_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, new_selector: CpuClkConfig) {
            let old_selector = clocks.cpu_clk.replace(new_selector);
            match new_selector {
                CpuClkConfig::Xtal => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_clk(clocks, CryptoClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::Xtal);
                }
                CpuClkConfig::RcFast => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_clk(clocks, CryptoClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::RcFast);
                }
                CpuClkConfig::Pll => {
                    configure_apb_clk(clocks, ApbClkConfig::Pll80m);
                    configure_crypto_clk(clocks, CryptoClkConfig::Pll160m);
                }
            }
            match new_selector {
                CpuClkConfig::Xtal => request_system_pre_div(clocks),
                CpuClkConfig::RcFast => request_system_pre_div(clocks),
                CpuClkConfig::Pll => request_cpu_pll_div_out(clocks),
            }
            configure_cpu_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuClkConfig::Xtal => release_system_pre_div(clocks),
                    CpuClkConfig::RcFast => release_system_pre_div(clocks),
                    CpuClkConfig::Pll => release_cpu_pll_div_out(clocks),
                }
            }
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        fn request_cpu_clk(_clocks: &mut ClockTree) {}
        fn release_cpu_clk(_clocks: &mut ClockTree) {}
        #[allow(unused_variables)]
        pub fn cpu_clk_config_frequency(clocks: &mut ClockTree, config: CpuClkConfig) -> u32 {
            match config {
                CpuClkConfig::Xtal => system_pre_div_frequency(clocks),
                CpuClkConfig::RcFast => system_pre_div_frequency(clocks),
                CpuClkConfig::Pll => cpu_pll_div_out_frequency(clocks),
            }
        }
        pub fn cpu_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.cpu_clk {
                cpu_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn request_pll_80m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_80M");
            trace!("Enabling PLL_80M");
            request_cpu_clk(clocks);
            enable_pll_80m_impl(clocks, true);
        }
        pub fn release_pll_80m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_80M");
            trace!("Disabling PLL_80M");
            enable_pll_80m_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn pll_80m_frequency(clocks: &mut ClockTree) -> u32 {
            80000000
        }
        pub fn request_pll_160m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_160M");
            trace!("Enabling PLL_160M");
            request_cpu_clk(clocks);
            enable_pll_160m_impl(clocks, true);
        }
        pub fn release_pll_160m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_160M");
            trace!("Disabling PLL_160M");
            enable_pll_160m_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn pll_160m_frequency(clocks: &mut ClockTree) -> u32 {
            160000000
        }
        pub fn configure_rc_fast_clk_div_n(clocks: &mut ClockTree, config: RcFastClkDivNConfig) {
            let old_config = clocks.rc_fast_clk_div_n.replace(config);
            configure_rc_fast_clk_div_n_impl(clocks, old_config, config);
        }
        pub fn rc_fast_clk_div_n_config(clocks: &mut ClockTree) -> Option<RcFastClkDivNConfig> {
            clocks.rc_fast_clk_div_n
        }
        pub fn request_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK_DIV_N");
            trace!("Enabling RC_FAST_CLK_DIV_N");
            request_rc_fast_clk(clocks);
            enable_rc_fast_clk_div_n_impl(clocks, true);
        }
        pub fn release_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK_DIV_N");
            trace!("Disabling RC_FAST_CLK_DIV_N");
            enable_rc_fast_clk_div_n_impl(clocks, false);
            release_rc_fast_clk(clocks);
        }
        #[allow(unused_variables)]
        pub fn rc_fast_clk_div_n_config_frequency(
            clocks: &mut ClockTree,
            config: RcFastClkDivNConfig,
        ) -> u32 {
            (rc_fast_clk_frequency(clocks) / (config.divisor() + 1))
        }
        pub fn rc_fast_clk_div_n_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.rc_fast_clk_div_n {
                rc_fast_clk_div_n_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn request_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL_DIV_CLK");
            trace!("Enabling XTAL_DIV_CLK");
            request_xtal_clk(clocks);
            enable_xtal_div_clk_impl(clocks, true);
        }
        pub fn release_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL_DIV_CLK");
            trace!("Disabling XTAL_DIV_CLK");
            enable_xtal_div_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_div_clk_frequency(clocks: &mut ClockTree) -> u32 {
            (xtal_clk_frequency(clocks) / 2)
        }
        pub fn configure_rtc_slow_clk(clocks: &mut ClockTree, new_selector: RtcSlowClkConfig) {
            let old_selector = clocks.rtc_slow_clk.replace(new_selector);
            match new_selector {
                RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            configure_rtc_slow_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
                }
            }
        }
        pub fn rtc_slow_clk_config(clocks: &mut ClockTree) -> Option<RtcSlowClkConfig> {
            clocks.rtc_slow_clk
        }
        pub fn request_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_SLOW_CLK");
            trace!("Enabling RTC_SLOW_CLK");
            match unwrap!(clocks.rtc_slow_clk) {
                RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            enable_rtc_slow_clk_impl(clocks, true);
        }
        pub fn release_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_SLOW_CLK");
            trace!("Disabling RTC_SLOW_CLK");
            enable_rtc_slow_clk_impl(clocks, false);
            match unwrap!(clocks.rtc_slow_clk) {
                RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
            }
        }
        #[allow(unused_variables)]
        pub fn rtc_slow_clk_config_frequency(
            clocks: &mut ClockTree,
            config: RtcSlowClkConfig,
        ) -> u32 {
            match config {
                RtcSlowClkConfig::Xtal32k => xtal32k_clk_frequency(clocks),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_frequency(clocks),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_frequency(clocks),
            }
        }
        pub fn rtc_slow_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.rtc_slow_clk {
                rtc_slow_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_rtc_fast_clk(clocks: &mut ClockTree, new_selector: RtcFastClkConfig) {
            let old_selector = clocks.rtc_fast_clk.replace(new_selector);
            if clocks.rtc_fast_clk_refcount > 0 {
                match new_selector {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
                configure_rtc_fast_clk_impl(clocks, old_selector, new_selector);
                if let Some(old_selector) = old_selector {
                    match old_selector {
                        RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                        RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                    }
                }
            } else {
                configure_rtc_fast_clk_impl(clocks, old_selector, new_selector);
            }
        }
        pub fn rtc_fast_clk_config(clocks: &mut ClockTree) -> Option<RtcFastClkConfig> {
            clocks.rtc_fast_clk
        }
        pub fn request_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_FAST_CLK");
            if increment_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Enabling RTC_FAST_CLK");
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
                enable_rtc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Disabling RTC_FAST_CLK");
                enable_rtc_fast_clk_impl(clocks, false);
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                }
            }
        }
        #[allow(unused_variables)]
        pub fn rtc_fast_clk_config_frequency(
            clocks: &mut ClockTree,
            config: RtcFastClkConfig,
        ) -> u32 {
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_frequency(clocks),
                RtcFastClkConfig::Rc => rc_fast_clk_div_n_frequency(clocks),
            }
        }
        pub fn rtc_fast_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.rtc_fast_clk {
                rtc_fast_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn configure_low_power_clk(clocks: &mut ClockTree, new_selector: LowPowerClkConfig) {
            let old_selector = clocks.low_power_clk.replace(new_selector);
            if clocks.low_power_clk_refcount > 0 {
                match new_selector {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LowPowerClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                configure_low_power_clk_impl(clocks, old_selector, new_selector);
                if let Some(old_selector) = old_selector {
                    match old_selector {
                        LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                        LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                        LowPowerClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                        LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                    }
                }
            } else {
                configure_low_power_clk_impl(clocks, old_selector, new_selector);
            }
        }
        pub fn low_power_clk_config(clocks: &mut ClockTree) -> Option<LowPowerClkConfig> {
            clocks.low_power_clk
        }
        pub fn request_low_power_clk(clocks: &mut ClockTree) {
            trace!("Requesting LOW_POWER_CLK");
            if increment_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Enabling LOW_POWER_CLK");
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LowPowerClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                enable_low_power_clk_impl(clocks, true);
            }
        }
        pub fn release_low_power_clk(clocks: &mut ClockTree) {
            trace!("Releasing LOW_POWER_CLK");
            if decrement_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Disabling LOW_POWER_CLK");
                enable_low_power_clk_impl(clocks, false);
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LowPowerClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        #[allow(unused_variables)]
        pub fn low_power_clk_config_frequency(
            clocks: &mut ClockTree,
            config: LowPowerClkConfig,
        ) -> u32 {
            match config {
                LowPowerClkConfig::Xtal => xtal_clk_frequency(clocks),
                LowPowerClkConfig::RcFast => rc_fast_clk_frequency(clocks),
                LowPowerClkConfig::Xtal32k => xtal32k_clk_frequency(clocks),
                LowPowerClkConfig::RtcSlow => rtc_slow_clk_frequency(clocks),
            }
        }
        pub fn low_power_clk_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.low_power_clk {
                low_power_clk_config_frequency(clocks, config)
            } else {
                0
            }
        }
        pub fn request_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Requesting UART_MEM_CLK");
            if increment_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Enabling UART_MEM_CLK");
                request_xtal_clk(clocks);
                enable_uart_mem_clk_impl(clocks, true);
            }
        }
        pub fn release_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Releasing UART_MEM_CLK");
            if decrement_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Disabling UART_MEM_CLK");
                enable_uart_mem_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn uart_mem_clk_frequency(clocks: &mut ClockTree) -> u32 {
            xtal_clk_frequency(clocks)
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            if clocks.timg_calibration_clock_refcount > 0 {
                match new_selector {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
                if let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                        TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                        TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                    }
                }
            } else {
                configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        #[allow(unused_variables)]
        pub fn timg_calibration_clock_config_frequency(
            clocks: &mut ClockTree,
            config: TimgCalibrationClockConfig,
        ) -> u32 {
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_frequency(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_frequency(clocks),
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_frequency(clocks),
            }
        }
        pub fn timg_calibration_clock_frequency(clocks: &mut ClockTree) -> u32 {
            if let Some(config) = clocks.timg_calibration_clock {
                timg_calibration_clock_config_frequency(clocks, config)
            } else {
                0
            }
        }
        impl RmtInstance {
            pub fn configure_sclk(self, clocks: &mut ClockTree, new_selector: RmtSclkConfig) {
                let old_selector = clocks.rmt_sclk[self as usize].replace(new_selector);
                if clocks.rmt_sclk_refcount[self as usize] > 0 {
                    match new_selector {
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.configure_sclk_impl(clocks, old_selector, new_selector);
                    if let Some(old_selector) = old_selector {
                        match old_selector {
                            RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                            RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                            RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                        }
                    }
                } else {
                    self.configure_sclk_impl(clocks, old_selector, new_selector);
                }
            }
            pub fn sclk_config(self, clocks: &mut ClockTree) -> Option<RmtSclkConfig> {
                clocks.rmt_sclk[self as usize]
            }
            pub fn request_sclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::SCLK", self);
                if increment_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Enabling {:?}::SCLK", self);
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.enable_sclk_impl(clocks, true);
                }
            }
            pub fn release_sclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::SCLK", self);
                if decrement_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Disabling {:?}::SCLK", self);
                    self.enable_sclk_impl(clocks, false);
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            #[allow(unused_variables)]
            pub fn sclk_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: RmtSclkConfig,
            ) -> u32 {
                match config {
                    RmtSclkConfig::ApbClk => apb_clk_frequency(clocks),
                    RmtSclkConfig::RcFastClk => rc_fast_clk_frequency(clocks),
                    RmtSclkConfig::XtalClk => xtal_clk_frequency(clocks),
                }
            }
            pub fn sclk_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.rmt_sclk[self as usize] {
                    self.sclk_config_frequency(clocks, config)
                } else {
                    0
                }
            }
        }
        impl TimgInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgFunctionClockConfig,
            ) {
                let old_selector = clocks.timg_function_clock[self as usize].replace(new_selector);
                if clocks.timg_function_clock_refcount[self as usize] > 0 {
                    match new_selector {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => request_apb_clk(clocks),
                    }
                    self.configure_function_clock_impl(clocks, old_selector, new_selector);
                    if let Some(old_selector) = old_selector {
                        match old_selector {
                            TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                            TimgFunctionClockConfig::ApbClk => release_apb_clk(clocks),
                        }
                    }
                } else {
                    self.configure_function_clock_impl(clocks, old_selector, new_selector);
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<TimgFunctionClockConfig> {
                clocks.timg_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => request_apb_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => release_apb_clk(clocks),
                    }
                }
            }
            #[allow(unused_variables)]
            pub fn function_clock_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: TimgFunctionClockConfig,
            ) -> u32 {
                match config {
                    TimgFunctionClockConfig::XtalClk => xtal_clk_frequency(clocks),
                    TimgFunctionClockConfig::ApbClk => apb_clk_frequency(clocks),
                }
            }
            pub fn function_clock_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.timg_function_clock[self as usize] {
                    self.function_clock_config_frequency(clocks, config)
                } else {
                    0
                }
            }
            pub fn configure_wdt_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgWdtClockConfig,
            ) {
                let old_selector = clocks.timg_wdt_clock[self as usize].replace(new_selector);
                if clocks.timg_wdt_clock_refcount[self as usize] > 0 {
                    match new_selector {
                        TimgWdtClockConfig::ApbClk => request_apb_clk(clocks),
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.configure_wdt_clock_impl(clocks, old_selector, new_selector);
                    if let Some(old_selector) = old_selector {
                        match old_selector {
                            TimgWdtClockConfig::ApbClk => release_apb_clk(clocks),
                            TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                        }
                    }
                } else {
                    self.configure_wdt_clock_impl(clocks, old_selector, new_selector);
                }
            }
            pub fn wdt_clock_config(self, clocks: &mut ClockTree) -> Option<TimgWdtClockConfig> {
                clocks.timg_wdt_clock[self as usize]
            }
            pub fn request_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::WDT_CLOCK", self);
                if increment_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::WDT_CLOCK", self);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::ApbClk => request_apb_clk(clocks),
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.enable_wdt_clock_impl(clocks, true);
                }
            }
            pub fn release_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::WDT_CLOCK", self);
                if decrement_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::WDT_CLOCK", self);
                    self.enable_wdt_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::ApbClk => release_apb_clk(clocks),
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            #[allow(unused_variables)]
            pub fn wdt_clock_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: TimgWdtClockConfig,
            ) -> u32 {
                match config {
                    TimgWdtClockConfig::ApbClk => apb_clk_frequency(clocks),
                    TimgWdtClockConfig::XtalClk => xtal_clk_frequency(clocks),
                }
            }
            pub fn wdt_clock_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.timg_wdt_clock[self as usize] {
                    self.wdt_clock_config_frequency(clocks, config)
                } else {
                    0
                }
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                if clocks.uart_function_clock_refcount[self as usize] > 0 {
                    match config.sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                    self.configure_function_clock_impl(clocks, old_config, config);
                    if let Some(old_config) = old_config {
                        match old_config.sclk {
                            UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                            UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                            UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        }
                    }
                } else {
                    self.configure_function_clock_impl(clocks, old_config, config);
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                    }
                }
            }
            #[allow(unused_variables)]
            pub fn function_clock_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) -> u32 {
                (match config.sclk {
                    UartFunctionClockSclk::Apb => apb_clk_frequency(clocks),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(clocks),
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(clocks),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.uart_function_clock[self as usize] {
                    self.function_clock_config_frequency(clocks, config)
                } else {
                    0
                }
            }
            pub fn configure_mem_clock(self, clocks: &mut ClockTree, config: UartMemClockConfig) {
                let old_config = clocks.uart_mem_clock[self as usize].replace(config);
                self.configure_mem_clock_impl(clocks, old_config, config);
            }
            pub fn mem_clock_config(self, clocks: &mut ClockTree) -> Option<UartMemClockConfig> {
                clocks.uart_mem_clock[self as usize]
            }
            pub fn request_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MEM_CLOCK", self);
                if increment_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::MEM_CLOCK", self);
                    request_uart_mem_clk(clocks);
                    self.enable_mem_clock_impl(clocks, true);
                }
            }
            pub fn release_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MEM_CLOCK", self);
                if decrement_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::MEM_CLOCK", self);
                    self.enable_mem_clock_impl(clocks, false);
                    release_uart_mem_clk(clocks);
                }
            }
            #[allow(unused_variables)]
            pub fn mem_clock_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: UartMemClockConfig,
            ) -> u32 {
                uart_mem_clk_frequency(clocks)
            }
            pub fn mem_clock_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.uart_mem_clock[self as usize] {
                    self.mem_clock_config_frequency(clocks, config)
                } else {
                    0
                }
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            #[allow(unused_variables)]
            pub fn baud_rate_generator_config_frequency(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency(clocks) * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self, clocks: &mut ClockTree) -> u32 {
                if let Some(config) = clocks.uart_baud_rate_generator[self as usize] {
                    self.baud_rate_generator_config_frequency(clocks, config)
                } else {
                    0
                }
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `XTAL_CLK` configuration.
            pub xtal_clk: Option<XtalClkConfig>,
            /// `PLL_CLK` configuration.
            pub pll_clk: Option<PllClkConfig>,
            /// `SYSTEM_PRE_DIV` configuration.
            pub system_pre_div: Option<SystemPreDivConfig>,
            /// `CPU_PLL_DIV_OUT` configuration.
            pub cpu_pll_div_out: Option<CpuPllDivOutConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `RC_FAST_CLK_DIV_N` configuration.
            pub rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            /// `RTC_SLOW_CLK` configuration.
            pub rtc_slow_clk: Option<RtcSlowClkConfig>,
            /// `RTC_FAST_CLK` configuration.
            pub rtc_fast_clk: Option<RtcFastClkConfig>,
            /// `LOW_POWER_CLK` configuration.
            pub low_power_clk: Option<LowPowerClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self) {
                ClockTree::with(|clocks| {
                    if let Some(config) = self.xtal_clk {
                        configure_xtal_clk(clocks, config);
                    }
                    if let Some(config) = self.pll_clk {
                        configure_pll_clk(clocks, config);
                    }
                    if let Some(config) = self.system_pre_div {
                        configure_system_pre_div(clocks, config);
                    }
                    if let Some(config) = self.cpu_pll_div_out {
                        configure_cpu_pll_div_out(clocks, config);
                    }
                    if let Some(config) = self.cpu_clk {
                        configure_cpu_clk(clocks, config);
                    }
                    if let Some(config) = self.rc_fast_clk_div_n {
                        configure_rc_fast_clk_div_n(clocks, config);
                    }
                    if let Some(config) = self.rtc_slow_clk {
                        configure_rtc_slow_clk(clocks, config);
                    }
                    if let Some(config) = self.rtc_fast_clk {
                        configure_rtc_fast_clk(clocks, config);
                    }
                    if let Some(config) = self.low_power_clk {
                        configure_low_power_clk(clocks, config);
                    }
                    if let Some(config) = self.timg_calibration_clock {
                        configure_timg_calibration_clock(clocks, config);
                    }
                });
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AES peripheral clock signal
            Aes,
            /// APB_SAR_ADC peripheral clock signal
            ApbSarAdc,
            /// DMA peripheral clock signal
            Dma,
            /// DS peripheral clock signal
            Ds,
            /// HMAC peripheral clock signal
            Hmac,
            /// I2C_EXT0 peripheral clock signal
            I2cExt0,
            /// I2S0 peripheral clock signal
            I2s0,
            /// LEDC peripheral clock signal
            Ledc,
            /// RMT peripheral clock signal
            Rmt,
            /// RSA peripheral clock signal
            Rsa,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SYSTIMER peripheral clock signal
            Systimer,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TIMG1 peripheral clock signal
            Timg1,
            /// TSENS peripheral clock signal
            Tsens,
            /// TWAI0 peripheral clock signal
            Twai0,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART_MEM peripheral clock signal
            UartMem,
            /// UHCI0 peripheral clock signal
            Uhci0,
            /// USB_DEVICE peripheral clock signal
            UsbDevice,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] = &[
                Self::Systimer,
                Self::Timg0,
                Self::Uart0,
                Self::UartMem,
                Self::UsbDevice,
            ];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::Aes,
                Self::ApbSarAdc,
                Self::Dma,
                Self::Ds,
                Self::Hmac,
                Self::I2cExt0,
                Self::I2s0,
                Self::Ledc,
                Self::Rmt,
                Self::Rsa,
                Self::Sha,
                Self::Spi2,
                Self::Systimer,
                Self::Timg0,
                Self::Timg1,
                Self::Tsens,
                Self::Twai0,
                Self::Uart0,
                Self::Uart1,
                Self::UartMem,
                Self::Uhci0,
                Self::UsbDevice,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_aes_clk_en().bit(enable));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.apb_saradc_clk_en().bit(enable));
                }
                Peripheral::Dma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.dma_clk_en().bit(enable));
                }
                Peripheral::Ds => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_ds_clk_en().bit(enable));
                }
                Peripheral::Hmac => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_hmac_clk_en().bit(enable));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2c_ext0_clk_en().bit(enable));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2s0_clk_en().bit(enable));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.ledc_clk_en().bit(enable));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.rmt_clk_en().bit(enable));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_rsa_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_sha_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.spi2_clk_en().bit(enable));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.systimer_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.timergroup_clk_en().bit(enable));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.timergroup1_clk_en().bit(enable));
                }
                Peripheral::Tsens => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.tsens_clk_en().bit(enable));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.twai_clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart1_clk_en().bit(enable));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_mem_clk_en().bit(enable));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uhci0_clk_en().bit(enable));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.usb_device_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_aes_rst().bit(reset));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.apb_saradc_rst().bit(reset));
                }
                Peripheral::Dma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.dma_rst().bit(reset));
                }
                Peripheral::Ds => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_ds_rst().bit(reset));
                }
                Peripheral::Hmac => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_hmac_rst().bit(reset));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2c_ext0_rst().bit(reset));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2s0_rst().bit(reset));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.ledc_rst().bit(reset));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.rmt_rst().bit(reset));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_rsa_rst().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_sha_rst().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.spi2_rst().bit(reset));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.systimer_rst().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.timergroup_rst().bit(reset));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.timergroup1_rst().bit(reset));
                }
                Peripheral::Tsens => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.tsens_rst().bit(reset));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.twai_rst().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_rst().bit(reset));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart1_rst().bit(reset));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_mem_rst().bit(reset));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uhci0_rst().bit(reset));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.usb_device_rst().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x3FC80000..0x3FCE0000
    };
    (size as str, "DRAM") => {
        "393216"
    };
    ("DRAM2_UNINIT") => {
        0x3FCCE400..0x3FCDE710
    };
    (size as str, "DRAM2_UNINIT") => {
        "66320"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)); _for_each_inner_i2c_master!((all(0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS));
        _for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS));
        _for_each_inner_uart!((all(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS), (1,
        UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1,
        FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD], true));
        _for_each_inner_spi_master!((all(SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2,
        FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0));
        _for_each_inner_spi_slave!((all(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO1 peripheral singleton"]
        GPIO1 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO3 peripheral singleton"]
        GPIO3 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO10 peripheral singleton"]
        GPIO10 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO18 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO18 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO19 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO21 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO21 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "AES peripheral singleton"] AES
        <= AES(AES : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "ASSIST_DEBUG peripheral singleton"] ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "BB peripheral singleton"] BB <=
        BB() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "DMA peripheral singleton"] DMA <= DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DS peripheral singleton"] DS <=
        DS() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EXTMEM peripheral singleton"]
        EXTMEM <= EXTMEM() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "FE peripheral singleton"] FE <= FE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FE2 peripheral singleton"] FE2
        <= FE2() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO_SD peripheral singleton"]
        GPIO_SD <= GPIO_SD() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "HMAC peripheral singleton"] HMAC <= HMAC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C0 peripheral singleton"]
        I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LEDC peripheral singleton"]
        LEDC <= LEDC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "NRX peripheral singleton"] NRX <= NRX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RMT peripheral singleton"] RMT
        <= RMT() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RNG peripheral singleton"] RNG <= RNG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RSA peripheral singleton"] RSA
        <= RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LPWR peripheral singleton"] LPWR <= RTC_CNTL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "SENSITIVE peripheral singleton"] SENSITIVE <= SENSITIVE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SHA peripheral singleton"] SHA
        <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTEM peripheral singleton"]
        SYSTEM <= SYSTEM() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG0 peripheral singleton"]
        TIMG0 <= TIMG0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TIMG1 peripheral singleton"] TIMG1 <= TIMG1() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TWAI0 peripheral singleton"]
        TWAI0 <= TWAI0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART0 peripheral singleton"] UART0 <= UART0(UART0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UHCI0 peripheral singleton"] UHCI0 <= UHCI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "XTS_AES peripheral singleton"] XTS_AES <= XTS_AES() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH2 peripheral singleton"]
        DMA_CH2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ADC2 peripheral singleton"]
        ADC2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "BT peripheral singleton"] BT <= virtual(BT_BB : { bind_bb_interrupt,
        enable_bb_interrupt, disable_bb_interrupt }, RWBLE : { bind_rwble_interrupt,
        enable_rwble_interrupt, disable_rwble_interrupt }, RWBT : { bind_rwbt_interrupt,
        enable_rwbt_interrupt, disable_rwbt_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FLASH peripheral singleton"]
        FLASH <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "SW_INTERRUPT peripheral singleton"] SW_INTERRUPT <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TSENS peripheral singleton"]
        TSENS <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "WIFI peripheral singleton"] WIFI <= virtual(WIFI_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt,
        enable_pwr_interrupt, disable_pwr_interrupt })));
        _for_each_inner_peripheral!((GPIO0)); _for_each_inner_peripheral!((GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14)); _for_each_inner_peripheral!((GPIO15));
        _for_each_inner_peripheral!((GPIO16)); _for_each_inner_peripheral!((GPIO17));
        _for_each_inner_peripheral!((GPIO18)); _for_each_inner_peripheral!((GPIO19));
        _for_each_inner_peripheral!((GPIO20)); _for_each_inner_peripheral!((GPIO21));
        _for_each_inner_peripheral!((AES(unstable)));
        _for_each_inner_peripheral!((APB_CTRL(unstable)));
        _for_each_inner_peripheral!((APB_SARADC(unstable)));
        _for_each_inner_peripheral!((ASSIST_DEBUG(unstable)));
        _for_each_inner_peripheral!((BB(unstable)));
        _for_each_inner_peripheral!((DMA(unstable)));
        _for_each_inner_peripheral!((DS(unstable)));
        _for_each_inner_peripheral!((EXTMEM(unstable)));
        _for_each_inner_peripheral!((FE(unstable)));
        _for_each_inner_peripheral!((FE2(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((GPIO_SD(unstable)));
        _for_each_inner_peripheral!((HMAC(unstable)));
        _for_each_inner_peripheral!((I2C_ANA_MST(unstable)));
        _for_each_inner_peripheral!((I2C0));
        _for_each_inner_peripheral!((I2S0(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LEDC(unstable)));
        _for_each_inner_peripheral!((NRX(unstable)));
        _for_each_inner_peripheral!((RMT(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((RSA(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((SENSITIVE(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((SPI0(unstable)));
        _for_each_inner_peripheral!((SPI1(unstable)));
        _for_each_inner_peripheral!((SPI2));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((SYSTIMER(unstable)));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((TIMG1(unstable)));
        _for_each_inner_peripheral!((TWAI0(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((UHCI0(unstable)));
        _for_each_inner_peripheral!((USB_DEVICE(unstable)));
        _for_each_inner_peripheral!((XTS_AES(unstable)));
        _for_each_inner_peripheral!((DMA_CH0(unstable)));
        _for_each_inner_peripheral!((DMA_CH1(unstable)));
        _for_each_inner_peripheral!((DMA_CH2(unstable)));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((ADC2(unstable)));
        _for_each_inner_peripheral!((BT(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((GPIO_DEDICATED(unstable)));
        _for_each_inner_peripheral!((SW_INTERRUPT(unstable)));
        _for_each_inner_peripheral!((TSENS(unstable)));
        _for_each_inner_peripheral!((WIFI)); _for_each_inner_peripheral!((SPI2, Spi2,
        0)); _for_each_inner_peripheral!((UHCI0, Uhci0, 2));
        _for_each_inner_peripheral!((I2S0, I2s0, 3)); _for_each_inner_peripheral!((AES,
        Aes, 6)); _for_each_inner_peripheral!((SHA, Sha, 7));
        _for_each_inner_peripheral!((APB_SARADC, ApbSaradc, 8));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "GPIO21 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO21 <= virtual()), (@ peri_type #[doc =
        "AES peripheral singleton"] AES <= AES(AES : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)), (@
        peri_type #[doc = "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC()
        (unstable)), (@ peri_type #[doc = "ASSIST_DEBUG peripheral singleton"]
        ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (@ peri_type #[doc =
        "BB peripheral singleton"] BB <= BB() (unstable)), (@ peri_type #[doc =
        "DMA peripheral singleton"] DMA <= DMA() (unstable)), (@ peri_type #[doc =
        "DS peripheral singleton"] DS <= DS() (unstable)), (@ peri_type #[doc =
        "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)), (@ peri_type #[doc =
        "EXTMEM peripheral singleton"] EXTMEM <= EXTMEM() (unstable)), (@ peri_type #[doc
        = "FE peripheral singleton"] FE <= FE() (unstable)), (@ peri_type #[doc =
        "FE2 peripheral singleton"] FE2 <= FE2() (unstable)), (@ peri_type #[doc =
        "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)), (@ peri_type #[doc =
        "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD() (unstable)), (@ peri_type
        #[doc = "HMAC peripheral singleton"] HMAC <= HMAC() (unstable)), (@ peri_type
        #[doc = "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST()
        (unstable)), (@ peri_type #[doc = "I2C0 peripheral singleton"] I2C0 <=
        I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "I2S0 peripheral singleton"]
        I2S0 <= I2S0(I2S0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable)), (@ peri_type #[doc = "IO_MUX peripheral singleton"] IO_MUX <=
        IO_MUX() (unstable)), (@ peri_type #[doc = "LEDC peripheral singleton"] LEDC <=
        LEDC() (unstable)), (@ peri_type #[doc = "NRX peripheral singleton"] NRX <= NRX()
        (unstable)), (@ peri_type #[doc = "RMT peripheral singleton"] RMT <= RMT()
        (unstable)), (@ peri_type #[doc = "RNG peripheral singleton"] RNG <= RNG()
        (unstable)), (@ peri_type #[doc = "RSA peripheral singleton"] RSA <= RSA(RSA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "LPWR peripheral singleton"] LPWR <= RTC_CNTL()
        (unstable)), (@ peri_type #[doc = "SENSITIVE peripheral singleton"] SENSITIVE <=
        SENSITIVE() (unstable)), (@ peri_type #[doc = "SHA peripheral singleton"] SHA <=
        SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "SPI0 peripheral singleton"] SPI0 <= SPI0()
        (unstable)), (@ peri_type #[doc = "SPI1 peripheral singleton"] SPI1 <= SPI1()
        (unstable)), (@ peri_type #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2
        : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <= SYSTEM() (unstable)),
        (@ peri_type #[doc = "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER()
        (unstable)), (@ peri_type #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0()
        (unstable)), (@ peri_type #[doc = "TIMG1 peripheral singleton"] TIMG1 <= TIMG1()
        (unstable)), (@ peri_type #[doc = "TWAI0 peripheral singleton"] TWAI0 <= TWAI0()
        (unstable)), (@ peri_type #[doc = "UART0 peripheral singleton"] UART0 <=
        UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UHCI0 peripheral singleton"]
        UHCI0 <= UHCI0() (unstable)), (@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "XTS_AES peripheral singleton"] XTS_AES <=
        XTS_AES() (unstable)), (@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual() (unstable)), (@ peri_type #[doc =
        "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual() (unstable)), (@ peri_type
        #[doc = "DMA_CH2 peripheral singleton"] DMA_CH2 <= virtual() (unstable)), (@
        peri_type #[doc = "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)), (@
        peri_type #[doc = "ADC2 peripheral singleton"] ADC2 <= virtual() (unstable)), (@
        peri_type #[doc = "BT peripheral singleton"] BT <= virtual(BT_BB : {
        bind_bb_interrupt, enable_bb_interrupt, disable_bb_interrupt }, RWBLE : {
        bind_rwble_interrupt, enable_rwble_interrupt, disable_rwble_interrupt }, RWBT : {
        bind_rwbt_interrupt, enable_rwbt_interrupt, disable_rwbt_interrupt })
        (unstable)), (@ peri_type #[doc = "FLASH peripheral singleton"] FLASH <=
        virtual() (unstable)), (@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)),
        (@ peri_type #[doc = "SW_INTERRUPT peripheral singleton"] SW_INTERRUPT <=
        virtual() (unstable)), (@ peri_type #[doc = "TSENS peripheral singleton"] TSENS
        <= virtual() (unstable)), (@ peri_type #[doc = "WIFI peripheral singleton"] WIFI
        <= virtual(WIFI_MAC : { bind_mac_interrupt, enable_mac_interrupt,
        disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt, enable_pwr_interrupt,
        disable_pwr_interrupt })))); _for_each_inner_peripheral!((singletons(GPIO0),
        (GPIO1), (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6), (GPIO7), (GPIO8), (GPIO9),
        (GPIO10), (GPIO11), (GPIO12), (GPIO13), (GPIO14), (GPIO15), (GPIO16), (GPIO17),
        (GPIO18), (GPIO19), (GPIO20), (GPIO21), (AES(unstable)), (APB_CTRL(unstable)),
        (APB_SARADC(unstable)), (ASSIST_DEBUG(unstable)), (BB(unstable)),
        (DMA(unstable)), (DS(unstable)), (EXTMEM(unstable)), (FE(unstable)),
        (FE2(unstable)), (GPIO(unstable)), (GPIO_SD(unstable)), (HMAC(unstable)),
        (I2C_ANA_MST(unstable)), (I2C0), (I2S0(unstable)), (INTERRUPT_CORE0(unstable)),
        (IO_MUX(unstable)), (LEDC(unstable)), (NRX(unstable)), (RMT(unstable)),
        (RNG(unstable)), (RSA(unstable)), (LPWR(unstable)), (SENSITIVE(unstable)),
        (SHA(unstable)), (SPI0(unstable)), (SPI1(unstable)), (SPI2), (SYSTEM(unstable)),
        (SYSTIMER(unstable)), (TIMG0(unstable)), (TIMG1(unstable)), (TWAI0(unstable)),
        (UART0), (UART1), (UHCI0(unstable)), (USB_DEVICE(unstable)), (XTS_AES(unstable)),
        (DMA_CH0(unstable)), (DMA_CH1(unstable)), (DMA_CH2(unstable)), (ADC1(unstable)),
        (ADC2(unstable)), (BT(unstable)), (FLASH(unstable)), (GPIO_DEDICATED(unstable)),
        (SW_INTERRUPT(unstable)), (TSENS(unstable)), (WIFI)));
        _for_each_inner_peripheral!((dma_eligible(SPI2, Spi2, 0), (UHCI0, Uhci0, 2),
        (I2S0, I2s0, 3), (AES, Aes, 6), (SHA, Sha, 7), (APB_SARADC, ApbSaradc, 8)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output])));
        _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3() () ([Input] [Output])));
        _for_each_inner_gpio!((4, GPIO4(_0 => MTMS _2 => FSPIHD) (_2 => FSPIHD) ([Input]
        [Output]))); _for_each_inner_gpio!((5, GPIO5(_0 => MTDI _2 => FSPIWP) (_2 =>
        FSPIWP) ([Input] [Output]))); _for_each_inner_gpio!((6, GPIO6(_0 => MTCK _2 =>
        FSPICLK) (_2 => FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((7, GPIO7(_2
        => FSPID) (_0 => MTDO _2 => FSPID) ([Input] [Output])));
        _for_each_inner_gpio!((8, GPIO8() () ([Input] [Output])));
        _for_each_inner_gpio!((9, GPIO9() () ([Input] [Output])));
        _for_each_inner_gpio!((10, GPIO10(_2 => FSPICS0) (_2 => FSPICS0) ([Input]
        [Output]))); _for_each_inner_gpio!((11, GPIO11() () ([Input] [Output])));
        _for_each_inner_gpio!((12, GPIO12(_0 => SPIHD) (_0 => SPIHD) ([Input]
        [Output]))); _for_each_inner_gpio!((13, GPIO13(_0 => SPIWP) (_0 => SPIWP)
        ([Input] [Output]))); _for_each_inner_gpio!((14, GPIO14() (_0 => SPICS0) ([Input]
        [Output]))); _for_each_inner_gpio!((15, GPIO15() (_0 => SPICLK) ([Input]
        [Output]))); _for_each_inner_gpio!((16, GPIO16(_0 => SPID) (_0 => SPID) ([Input]
        [Output]))); _for_each_inner_gpio!((17, GPIO17(_0 => SPIQ) (_0 => SPIQ) ([Input]
        [Output]))); _for_each_inner_gpio!((18, GPIO18() () ([Input] [Output])));
        _for_each_inner_gpio!((19, GPIO19() () ([Input] [Output])));
        _for_each_inner_gpio!((20, GPIO20(_0 => U0RXD) () ([Input] [Output])));
        _for_each_inner_gpio!((21, GPIO21() (_0 => U0TXD) ([Input] [Output])));
        _for_each_inner_gpio!((all(0, GPIO0() () ([Input] [Output])), (1, GPIO1() ()
        ([Input] [Output])), (2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input] [Output])),
        (3, GPIO3() () ([Input] [Output])), (4, GPIO4(_0 => MTMS _2 => FSPIHD) (_2 =>
        FSPIHD) ([Input] [Output])), (5, GPIO5(_0 => MTDI _2 => FSPIWP) (_2 => FSPIWP)
        ([Input] [Output])), (6, GPIO6(_0 => MTCK _2 => FSPICLK) (_2 => FSPICLK) ([Input]
        [Output])), (7, GPIO7(_2 => FSPID) (_0 => MTDO _2 => FSPID) ([Input] [Output])),
        (8, GPIO8() () ([Input] [Output])), (9, GPIO9() () ([Input] [Output])), (10,
        GPIO10(_2 => FSPICS0) (_2 => FSPICS0) ([Input] [Output])), (11, GPIO11() ()
        ([Input] [Output])), (12, GPIO12(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output])),
        (13, GPIO13(_0 => SPIWP) (_0 => SPIWP) ([Input] [Output])), (14, GPIO14() (_0 =>
        SPICS0) ([Input] [Output])), (15, GPIO15() (_0 => SPICLK) ([Input] [Output])),
        (16, GPIO16(_0 => SPID) (_0 => SPID) ([Input] [Output])), (17, GPIO17(_0 => SPIQ)
        (_0 => SPIQ) ([Input] [Output])), (18, GPIO18() () ([Input] [Output])), (19,
        GPIO19() () ([Input] [Output])), (20, GPIO20(_0 => U0RXD) () ([Input] [Output])),
        (21, GPIO21() (_0 => U0TXD) ([Input] [Output]))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - `all_expanded`: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs. For example, in case of `ADC2_CH3` the expanded form looks like
///   `(ADC2_CH3, ADCn_CHm, 2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((ADC1_CH0, GPIO0));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO1));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO2));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO3));
        _for_each_inner_analog_function!((ADC1_CH4, GPIO4));
        _for_each_inner_analog_function!((ADC2_CH0, GPIO5));
        _for_each_inner_analog_function!((USB_DM, GPIO18));
        _for_each_inner_analog_function!((USB_DP, GPIO19));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO0));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO1));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO2));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO3));
        _for_each_inner_analog_function!(((ADC1_CH4, ADCn_CHm, 1, 4), GPIO4));
        _for_each_inner_analog_function!(((ADC2_CH0, ADCn_CHm, 2, 0), GPIO5));
        _for_each_inner_analog_function!((all(ADC1_CH0, GPIO0), (ADC1_CH1, GPIO1),
        (ADC1_CH2, GPIO2), (ADC1_CH3, GPIO3), (ADC1_CH4, GPIO4), (ADC2_CH0, GPIO5),
        (USB_DM, GPIO18), (USB_DP, GPIO19)));
        _for_each_inner_analog_function!((all_expanded((ADC1_CH0, ADCn_CHm, 1, 0),
        GPIO0), ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO1), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO2),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO3), ((ADC1_CH4, ADCn_CHm, 1, 4), GPIO4),
        ((ADC2_CH0, ADCn_CHm, 2, 0), GPIO5)));
    };
}
/// This macro can be used to generate code for each LP/RTC function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - `all_expanded`: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs. For example, in case of `SAR_I2C_SCL_1` the expanded form looks like
///   `(SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(RTC_GPIO15, GPIO12)`
/// - `((RTC_GPIO15, RTC_GPIOn, 15), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((RTC_GPIO0, GPIO0));
        _for_each_inner_lp_function!((RTC_GPIO1, GPIO1));
        _for_each_inner_lp_function!((RTC_GPIO2, GPIO2));
        _for_each_inner_lp_function!((RTC_GPIO3, GPIO3));
        _for_each_inner_lp_function!((RTC_GPIO4, GPIO4));
        _for_each_inner_lp_function!((RTC_GPIO5, GPIO5));
        _for_each_inner_lp_function!(((RTC_GPIO0, RTC_GPIOn, 0), GPIO0));
        _for_each_inner_lp_function!(((RTC_GPIO1, RTC_GPIOn, 1), GPIO1));
        _for_each_inner_lp_function!(((RTC_GPIO2, RTC_GPIOn, 2), GPIO2));
        _for_each_inner_lp_function!(((RTC_GPIO3, RTC_GPIOn, 3), GPIO3));
        _for_each_inner_lp_function!(((RTC_GPIO4, RTC_GPIOn, 4), GPIO4));
        _for_each_inner_lp_function!(((RTC_GPIO5, RTC_GPIOn, 5), GPIO5));
        _for_each_inner_lp_function!((all(RTC_GPIO0, GPIO0), (RTC_GPIO1, GPIO1),
        (RTC_GPIO2, GPIO2), (RTC_GPIO3, GPIO3), (RTC_GPIO4, GPIO4), (RTC_GPIO5, GPIO5)));
        _for_each_inner_lp_function!((all_expanded((RTC_GPIO0, RTC_GPIOn, 0), GPIO0),
        ((RTC_GPIO1, RTC_GPIOn, 1), GPIO1), ((RTC_GPIO2, RTC_GPIOn, 2), GPIO2),
        ((RTC_GPIO3, RTC_GPIOn, 3), GPIO3), ((RTC_GPIO4, RTC_GPIOn, 4), GPIO4),
        ((RTC_GPIO5, RTC_GPIOn, 5), GPIO5)));
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            SPIQ             = 0,
            SPID             = 1,
            SPIHD            = 2,
            SPIWP            = 3,
            U0RXD            = 6,
            U0CTS            = 7,
            U0DSR            = 8,
            U1RXD            = 9,
            U1CTS            = 10,
            U1DSR            = 11,
            I2S_MCLK         = 12,
            I2SO_BCK         = 13,
            I2SO_WS          = 14,
            I2SI_SD          = 15,
            I2SI_BCK         = 16,
            I2SI_WS          = 17,
            GPIO_BT_PRIORITY = 18,
            GPIO_BT_ACTIVE   = 19,
            CPU_GPIO_0       = 28,
            CPU_GPIO_1       = 29,
            CPU_GPIO_2       = 30,
            CPU_GPIO_3       = 31,
            CPU_GPIO_4       = 32,
            CPU_GPIO_5       = 33,
            CPU_GPIO_6       = 34,
            CPU_GPIO_7       = 35,
            EXT_ADC_START    = 45,
            RMT_SIG_0        = 51,
            RMT_SIG_1        = 52,
            I2CEXT0_SCL      = 53,
            I2CEXT0_SDA      = 54,
            FSPICLK          = 63,
            FSPIQ            = 64,
            FSPID            = 65,
            FSPIHD           = 66,
            FSPIWP           = 67,
            FSPICS0          = 68,
            TWAI_RX          = 74,
            SIG_FUNC_97      = 97,
            SIG_FUNC_98      = 98,
            SIG_FUNC_99      = 99,
            SIG_FUNC_100     = 100,
            MTCK,
            MTMS,
            MTDI,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            SPIQ             = 0,
            SPID             = 1,
            SPIHD            = 2,
            SPIWP            = 3,
            SPICLK           = 4,
            SPICS0           = 5,
            U0TXD            = 6,
            U0RTS            = 7,
            U0DTR            = 8,
            U1TXD            = 9,
            U1RTS            = 10,
            U1DTR            = 11,
            I2S_MCLK         = 12,
            I2SO_BCK         = 13,
            I2SO_WS          = 14,
            I2SO_SD          = 15,
            I2SI_BCK         = 16,
            I2SI_WS          = 17,
            GPIO_WLAN_PRIO   = 18,
            GPIO_WLAN_ACTIVE = 19,
            CPU_GPIO_0       = 28,
            CPU_GPIO_1       = 29,
            CPU_GPIO_2       = 30,
            CPU_GPIO_3       = 31,
            CPU_GPIO_4       = 32,
            CPU_GPIO_5       = 33,
            CPU_GPIO_6       = 34,
            CPU_GPIO_7       = 35,
            USB_JTAG_TCK     = 36,
            USB_JTAG_TMS     = 37,
            USB_JTAG_TDI     = 38,
            USB_JTAG_TDO     = 39,
            LEDC_LS_SIG0     = 45,
            LEDC_LS_SIG1     = 46,
            LEDC_LS_SIG2     = 47,
            LEDC_LS_SIG3     = 48,
            LEDC_LS_SIG4     = 49,
            LEDC_LS_SIG5     = 50,
            RMT_SIG_0        = 51,
            RMT_SIG_1        = 52,
            I2CEXT0_SCL      = 53,
            I2CEXT0_SDA      = 54,
            GPIO_SD0         = 55,
            GPIO_SD1         = 56,
            GPIO_SD2         = 57,
            GPIO_SD3         = 58,
            I2SO_SD1         = 59,
            FSPICLK          = 63,
            FSPIQ            = 64,
            FSPID            = 65,
            FSPIHD           = 66,
            FSPIWP           = 67,
            FSPICS0          = 68,
            FSPICS1          = 69,
            FSPICS3          = 70,
            FSPICS2          = 71,
            FSPICS4          = 72,
            FSPICS5          = 73,
            TWAI_TX          = 74,
            TWAI_BUS_OFF_ON  = 75,
            TWAI_CLKOUT      = 76,
            ANT_SEL0         = 89,
            ANT_SEL1         = 90,
            ANT_SEL2         = 91,
            ANT_SEL3         = 92,
            ANT_SEL4         = 93,
            ANT_SEL5         = 94,
            ANT_SEL6         = 95,
            ANT_SEL7         = 96,
            SIG_FUNC_97      = 97,
            SIG_FUNC_98      = 98,
            SIG_FUNC_99      = 99,
            SIG_FUNC_100     = 100,
            CLK_OUT1         = 123,
            CLK_OUT2         = 124,
            CLK_OUT3         = 125,
            SPICS1           = 126,
            USB_JTAG_TRST    = 127,
            GPIO             = 128,
            MTDO,
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO {
            crate::peripherals::IO_MUX::regs().gpio(gpio_num as usize)
        }
    };
}