#[doc = "Register `IEN` reader"]
pub struct R(crate::R<IEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IEN` writer"]
pub struct W(crate::W<IEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OF` reader - Overflow Interrupt Enable"]
pub type OF_R = crate::BitReader<bool>;
#[doc = "Field `OF` writer - Overflow Interrupt Enable"]
pub type OF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
#[doc = "Field `UF` reader - Underflow Interrupt Enable"]
pub type UF_R = crate::BitReader<bool>;
#[doc = "Field `UF` writer - Underflow Interrupt Enable"]
pub type UF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
#[doc = "Field `CC0` reader - CC Channel 0 Interrupt Enable"]
pub type CC0_R = crate::BitReader<bool>;
#[doc = "Field `CC0` writer - CC Channel 0 Interrupt Enable"]
pub type CC0_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
#[doc = "Field `CC1` reader - CC Channel 1 Interrupt Enable"]
pub type CC1_R = crate::BitReader<bool>;
#[doc = "Field `CC1` writer - CC Channel 1 Interrupt Enable"]
pub type CC1_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
#[doc = "Field `CC2` reader - CC Channel 2 Interrupt Enable"]
pub type CC2_R = crate::BitReader<bool>;
#[doc = "Field `CC2` writer - CC Channel 2 Interrupt Enable"]
pub type CC2_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
#[doc = "Field `ICBOF0` reader - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF0_R = crate::BitReader<bool>;
#[doc = "Field `ICBOF0` writer - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF0_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
#[doc = "Field `ICBOF1` reader - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF1_R = crate::BitReader<bool>;
#[doc = "Field `ICBOF1` writer - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF1_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 9>;
#[doc = "Field `ICBOF2` reader - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF2_R = crate::BitReader<bool>;
#[doc = "Field `ICBOF2` writer - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
pub type ICBOF2_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 10>;
impl R {
#[doc = "Bit 0 - Overflow Interrupt Enable"]
#[inline(always)]
pub fn of(&self) -> OF_R {
OF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Underflow Interrupt Enable"]
#[inline(always)]
pub fn uf(&self) -> UF_R {
UF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - CC Channel 0 Interrupt Enable"]
#[inline(always)]
pub fn cc0(&self) -> CC0_R {
CC0_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CC Channel 1 Interrupt Enable"]
#[inline(always)]
pub fn cc1(&self) -> CC1_R {
CC1_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CC Channel 2 Interrupt Enable"]
#[inline(always)]
pub fn cc2(&self) -> CC2_R {
CC2_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8 - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof0(&self) -> ICBOF0_R {
ICBOF0_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof1(&self) -> ICBOF1_R {
ICBOF1_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof2(&self) -> ICBOF2_R {
ICBOF2_R::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Overflow Interrupt Enable"]
#[inline(always)]
pub fn of(&mut self) -> OF_W {
OF_W::new(self)
}
#[doc = "Bit 1 - Underflow Interrupt Enable"]
#[inline(always)]
pub fn uf(&mut self) -> UF_W {
UF_W::new(self)
}
#[doc = "Bit 4 - CC Channel 0 Interrupt Enable"]
#[inline(always)]
pub fn cc0(&mut self) -> CC0_W {
CC0_W::new(self)
}
#[doc = "Bit 5 - CC Channel 1 Interrupt Enable"]
#[inline(always)]
pub fn cc1(&mut self) -> CC1_W {
CC1_W::new(self)
}
#[doc = "Bit 6 - CC Channel 2 Interrupt Enable"]
#[inline(always)]
pub fn cc2(&mut self) -> CC2_W {
CC2_W::new(self)
}
#[doc = "Bit 8 - CC Channel 0 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof0(&mut self) -> ICBOF0_W {
ICBOF0_W::new(self)
}
#[doc = "Bit 9 - CC Channel 1 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof1(&mut self) -> ICBOF1_W {
ICBOF1_W::new(self)
}
#[doc = "Bit 10 - CC Channel 2 Input Capture Buffer Overflow Interrupt Enable"]
#[inline(always)]
pub fn icbof2(&mut self) -> ICBOF2_W {
ICBOF2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
pub struct IEN_SPEC;
impl crate::RegisterSpec for IEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ien::R](R) reader structure"]
impl crate::Readable for IEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
impl crate::Writable for IEN_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets IEN to value 0"]
impl crate::Resettable for IEN_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}