efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

///Register `ROUTEPEN` reader
pub type R = crate::R<ROUTEPENrs>;
///Register `ROUTEPEN` writer
pub type W = crate::W<ROUTEPENrs>;
///Field `RXPEN` reader - RX Pin Enable
pub type RxpenR = crate::BitReader;
///Field `RXPEN` writer - RX Pin Enable
pub type RxpenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TXPEN` reader - TX Pin Enable
pub type TxpenR = crate::BitReader;
///Field `TXPEN` writer - TX Pin Enable
pub type TxpenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CSPEN` reader - CS Pin Enable
pub type CspenR = crate::BitReader;
///Field `CSPEN` writer - CS Pin Enable
pub type CspenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CLKPEN` reader - CLK Pin Enable
pub type ClkpenR = crate::BitReader;
///Field `CLKPEN` writer - CLK Pin Enable
pub type ClkpenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CTSPEN` reader - CTS Pin Enable
pub type CtspenR = crate::BitReader;
///Field `CTSPEN` writer - CTS Pin Enable
pub type CtspenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RTSPEN` reader - RTS Pin Enable
pub type RtspenR = crate::BitReader;
///Field `RTSPEN` writer - RTS Pin Enable
pub type RtspenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - RX Pin Enable
    #[inline(always)]
    pub fn rxpen(&self) -> RxpenR {
        RxpenR::new((self.bits & 1) != 0)
    }
    ///Bit 1 - TX Pin Enable
    #[inline(always)]
    pub fn txpen(&self) -> TxpenR {
        TxpenR::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - CS Pin Enable
    #[inline(always)]
    pub fn cspen(&self) -> CspenR {
        CspenR::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - CLK Pin Enable
    #[inline(always)]
    pub fn clkpen(&self) -> ClkpenR {
        ClkpenR::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - CTS Pin Enable
    #[inline(always)]
    pub fn ctspen(&self) -> CtspenR {
        CtspenR::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - RTS Pin Enable
    #[inline(always)]
    pub fn rtspen(&self) -> RtspenR {
        RtspenR::new(((self.bits >> 5) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ROUTEPEN")
            .field("rxpen", &self.rxpen())
            .field("txpen", &self.txpen())
            .field("cspen", &self.cspen())
            .field("clkpen", &self.clkpen())
            .field("ctspen", &self.ctspen())
            .field("rtspen", &self.rtspen())
            .finish()
    }
}
impl W {
    ///Bit 0 - RX Pin Enable
    #[inline(always)]
    pub fn rxpen(&mut self) -> RxpenW<'_, ROUTEPENrs> {
        RxpenW::new(self, 0)
    }
    ///Bit 1 - TX Pin Enable
    #[inline(always)]
    pub fn txpen(&mut self) -> TxpenW<'_, ROUTEPENrs> {
        TxpenW::new(self, 1)
    }
    ///Bit 2 - CS Pin Enable
    #[inline(always)]
    pub fn cspen(&mut self) -> CspenW<'_, ROUTEPENrs> {
        CspenW::new(self, 2)
    }
    ///Bit 3 - CLK Pin Enable
    #[inline(always)]
    pub fn clkpen(&mut self) -> ClkpenW<'_, ROUTEPENrs> {
        ClkpenW::new(self, 3)
    }
    ///Bit 4 - CTS Pin Enable
    #[inline(always)]
    pub fn ctspen(&mut self) -> CtspenW<'_, ROUTEPENrs> {
        CtspenW::new(self, 4)
    }
    ///Bit 5 - RTS Pin Enable
    #[inline(always)]
    pub fn rtspen(&mut self) -> RtspenW<'_, ROUTEPENrs> {
        RtspenW::new(self, 5)
    }
}
///I/O Routing Pin Enable Register
///
///You can [`read`](crate::Reg::read) this register and get [`routepen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`routepen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct ROUTEPENrs;
impl crate::RegisterSpec for ROUTEPENrs {
    type Ux = u32;
}
///`read()` method returns [`routepen::R`](R) reader structure
impl crate::Readable for ROUTEPENrs {}
///`write(|w| ..)` method takes [`routepen::W`](W) writer structure
impl crate::Writable for ROUTEPENrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets ROUTEPEN to value 0
impl crate::Resettable for ROUTEPENrs {}