efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

///Register `IEN` reader
pub type R = crate::R<IENrs>;
///Register `IEN` writer
pub type W = crate::W<IENrs>;
///Field `UF` reader - UF Interrupt Enable
pub type UfR = crate::BitReader;
///Field `UF` writer - UF Interrupt Enable
pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OF` reader - OF Interrupt Enable
pub type OfR = crate::BitReader;
///Field `OF` writer - OF Interrupt Enable
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DIRCNG` reader - DIRCNG Interrupt Enable
pub type DircngR = crate::BitReader;
///Field `DIRCNG` writer - DIRCNG Interrupt Enable
pub type DircngW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `AUXOF` reader - AUXOF Interrupt Enable
pub type AuxofR = crate::BitReader;
///Field `AUXOF` writer - AUXOF Interrupt Enable
pub type AuxofW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TCC` reader - TCC Interrupt Enable
pub type TccR = crate::BitReader;
///Field `TCC` writer - TCC Interrupt Enable
pub type TccW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OQSTERR` reader - OQSTERR Interrupt Enable
pub type OqsterrR = crate::BitReader;
///Field `OQSTERR` writer - OQSTERR Interrupt Enable
pub type OqsterrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - UF Interrupt Enable
    #[inline(always)]
    pub fn uf(&self) -> UfR {
        UfR::new((self.bits & 1) != 0)
    }
    ///Bit 1 - OF Interrupt Enable
    #[inline(always)]
    pub fn of(&self) -> OfR {
        OfR::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - DIRCNG Interrupt Enable
    #[inline(always)]
    pub fn dircng(&self) -> DircngR {
        DircngR::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - AUXOF Interrupt Enable
    #[inline(always)]
    pub fn auxof(&self) -> AuxofR {
        AuxofR::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - TCC Interrupt Enable
    #[inline(always)]
    pub fn tcc(&self) -> TccR {
        TccR::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - OQSTERR Interrupt Enable
    #[inline(always)]
    pub fn oqsterr(&self) -> OqsterrR {
        OqsterrR::new(((self.bits >> 5) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IEN")
            .field("uf", &self.uf())
            .field("of", &self.of())
            .field("dircng", &self.dircng())
            .field("auxof", &self.auxof())
            .field("tcc", &self.tcc())
            .field("oqsterr", &self.oqsterr())
            .finish()
    }
}
impl W {
    ///Bit 0 - UF Interrupt Enable
    #[inline(always)]
    pub fn uf(&mut self) -> UfW<'_, IENrs> {
        UfW::new(self, 0)
    }
    ///Bit 1 - OF Interrupt Enable
    #[inline(always)]
    pub fn of(&mut self) -> OfW<'_, IENrs> {
        OfW::new(self, 1)
    }
    ///Bit 2 - DIRCNG Interrupt Enable
    #[inline(always)]
    pub fn dircng(&mut self) -> DircngW<'_, IENrs> {
        DircngW::new(self, 2)
    }
    ///Bit 3 - AUXOF Interrupt Enable
    #[inline(always)]
    pub fn auxof(&mut self) -> AuxofW<'_, IENrs> {
        AuxofW::new(self, 3)
    }
    ///Bit 4 - TCC Interrupt Enable
    #[inline(always)]
    pub fn tcc(&mut self) -> TccW<'_, IENrs> {
        TccW::new(self, 4)
    }
    ///Bit 5 - OQSTERR Interrupt Enable
    #[inline(always)]
    pub fn oqsterr(&mut self) -> OqsterrW<'_, IENrs> {
        OqsterrW::new(self, 5)
    }
}
///Interrupt Enable Register
///
///You can [`read`](crate::Reg::read) this register and get [`ien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct IENrs;
impl crate::RegisterSpec for IENrs {
    type Ux = u32;
}
///`read()` method returns [`ien::R`](R) reader structure
impl crate::Readable for IENrs {}
///`write(|w| ..)` method takes [`ien::W`](W) writer structure
impl crate::Writable for IENrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets IEN to value 0
impl crate::Resettable for IENrs {}