efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

///Register `SADDRMASK` reader
pub type R = crate::R<SADDRMASKrs>;
///Register `SADDRMASK` writer
pub type W = crate::W<SADDRMASKrs>;
///Field `MASK` reader - Slave Address Mask
pub type MaskR = crate::FieldReader;
///Field `MASK` writer - Slave Address Mask
pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
    ///Bits 1:7 - Slave Address Mask
    #[inline(always)]
    pub fn mask(&self) -> MaskR {
        MaskR::new(((self.bits >> 1) & 0x7f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SADDRMASK")
            .field("mask", &self.mask())
            .finish()
    }
}
impl W {
    ///Bits 1:7 - Slave Address Mask
    #[inline(always)]
    pub fn mask(&mut self) -> MaskW<'_, SADDRMASKrs> {
        MaskW::new(self, 1)
    }
}
///Slave Address Mask Register
///
///You can [`read`](crate::Reg::read) this register and get [`saddrmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`saddrmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct SADDRMASKrs;
impl crate::RegisterSpec for SADDRMASKrs {
    type Ux = u32;
}
///`read()` method returns [`saddrmask::R`](R) reader structure
impl crate::Readable for SADDRMASKrs {}
///`write(|w| ..)` method takes [`saddrmask::W`](W) writer structure
impl crate::Writable for SADDRMASKrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets SADDRMASK to value 0
impl crate::Resettable for SADDRMASKrs {}