efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

///Register `CMD` writer
pub type W = crate::W<CMDrs>;
///Field `START` writer - Send Start Condition
pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `STOP` writer - Send Stop Condition
pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ACK` writer - Send ACK
pub type AckW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NACK` writer - Send NACK
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CONT` writer - Continue Transmission
pub type ContW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ABORT` writer - Abort Transmission
pub type AbortW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CLEARTX` writer - Clear TX
pub type CleartxW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CLEARPC` writer - Clear Pending Commands
pub type ClearpcW<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<CMDrs> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    ///Bit 0 - Send Start Condition
    #[inline(always)]
    pub fn start(&mut self) -> StartW<'_, CMDrs> {
        StartW::new(self, 0)
    }
    ///Bit 1 - Send Stop Condition
    #[inline(always)]
    pub fn stop(&mut self) -> StopW<'_, CMDrs> {
        StopW::new(self, 1)
    }
    ///Bit 2 - Send ACK
    #[inline(always)]
    pub fn ack(&mut self) -> AckW<'_, CMDrs> {
        AckW::new(self, 2)
    }
    ///Bit 3 - Send NACK
    #[inline(always)]
    pub fn nack(&mut self) -> NackW<'_, CMDrs> {
        NackW::new(self, 3)
    }
    ///Bit 4 - Continue Transmission
    #[inline(always)]
    pub fn cont(&mut self) -> ContW<'_, CMDrs> {
        ContW::new(self, 4)
    }
    ///Bit 5 - Abort Transmission
    #[inline(always)]
    pub fn abort(&mut self) -> AbortW<'_, CMDrs> {
        AbortW::new(self, 5)
    }
    ///Bit 6 - Clear TX
    #[inline(always)]
    pub fn cleartx(&mut self) -> CleartxW<'_, CMDrs> {
        CleartxW::new(self, 6)
    }
    ///Bit 7 - Clear Pending Commands
    #[inline(always)]
    pub fn clearpc(&mut self) -> ClearpcW<'_, CMDrs> {
        ClearpcW::new(self, 7)
    }
}
///Command Register
///
///You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct CMDrs;
impl crate::RegisterSpec for CMDrs {
    type Ux = u32;
}
///`write(|w| ..)` method takes [`cmd::W`](W) writer structure
impl crate::Writable for CMDrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CMD to value 0
impl crate::Resettable for CMDrs {}