efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106

///Register `ROUTEPEN` reader
pub type R = crate::R<ROUTEPENrs>;
///Register `ROUTEPEN` writer
pub type W = crate::W<ROUTEPENrs>;
///Field `SWCLKTCKPEN` reader - Serial Wire Clock and JTAG Test Clock Pin Enable
pub type SwclktckpenR = crate::BitReader;
///Field `SWCLKTCKPEN` writer - Serial Wire Clock and JTAG Test Clock Pin Enable
pub type SwclktckpenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SWDIOTMSPEN` reader - Serial Wire Data and JTAG Test Mode Select Pin Enable
pub type SwdiotmspenR = crate::BitReader;
///Field `SWDIOTMSPEN` writer - Serial Wire Data and JTAG Test Mode Select Pin Enable
pub type SwdiotmspenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TDOPEN` reader - JTAG Test Debug Output Pin Enable
pub type TdopenR = crate::BitReader;
///Field `TDOPEN` writer - JTAG Test Debug Output Pin Enable
pub type TdopenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TDIPEN` reader - JTAG Test Debug Input Pin Enable
pub type TdipenR = crate::BitReader;
///Field `TDIPEN` writer - JTAG Test Debug Input Pin Enable
pub type TdipenW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SWVPEN` reader - Serial Wire Viewer Output Pin Enable
pub type SwvpenR = crate::BitReader;
///Field `SWVPEN` writer - Serial Wire Viewer Output Pin Enable
pub type SwvpenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable
    #[inline(always)]
    pub fn swclktckpen(&self) -> SwclktckpenR {
        SwclktckpenR::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable
    #[inline(always)]
    pub fn swdiotmspen(&self) -> SwdiotmspenR {
        SwdiotmspenR::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - JTAG Test Debug Output Pin Enable
    #[inline(always)]
    pub fn tdopen(&self) -> TdopenR {
        TdopenR::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - JTAG Test Debug Input Pin Enable
    #[inline(always)]
    pub fn tdipen(&self) -> TdipenR {
        TdipenR::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - Serial Wire Viewer Output Pin Enable
    #[inline(always)]
    pub fn swvpen(&self) -> SwvpenR {
        SwvpenR::new(((self.bits >> 4) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ROUTEPEN")
            .field("swclktckpen", &self.swclktckpen())
            .field("swdiotmspen", &self.swdiotmspen())
            .field("tdopen", &self.tdopen())
            .field("tdipen", &self.tdipen())
            .field("swvpen", &self.swvpen())
            .finish()
    }
}
impl W {
    ///Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable
    #[inline(always)]
    pub fn swclktckpen(&mut self) -> SwclktckpenW<'_, ROUTEPENrs> {
        SwclktckpenW::new(self, 0)
    }
    ///Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable
    #[inline(always)]
    pub fn swdiotmspen(&mut self) -> SwdiotmspenW<'_, ROUTEPENrs> {
        SwdiotmspenW::new(self, 1)
    }
    ///Bit 2 - JTAG Test Debug Output Pin Enable
    #[inline(always)]
    pub fn tdopen(&mut self) -> TdopenW<'_, ROUTEPENrs> {
        TdopenW::new(self, 2)
    }
    ///Bit 3 - JTAG Test Debug Input Pin Enable
    #[inline(always)]
    pub fn tdipen(&mut self) -> TdipenW<'_, ROUTEPENrs> {
        TdipenW::new(self, 3)
    }
    ///Bit 4 - Serial Wire Viewer Output Pin Enable
    #[inline(always)]
    pub fn swvpen(&mut self) -> SwvpenW<'_, ROUTEPENrs> {
        SwvpenW::new(self, 4)
    }
}
///I/O Routing Pin Enable Register
///
///You can [`read`](crate::Reg::read) this register and get [`routepen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`routepen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct ROUTEPENrs;
impl crate::RegisterSpec for ROUTEPENrs {
    type Ux = u32;
}
///`read()` method returns [`routepen::R`](R) reader structure
impl crate::Readable for ROUTEPENrs {}
///`write(|w| ..)` method takes [`routepen::W`](W) writer structure
impl crate::Writable for ROUTEPENrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets ROUTEPEN to value 0x0f
impl crate::Resettable for ROUTEPENrs {
    const RESET_VALUE: u32 = 0x0f;
}