efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179

///Register `HFPERCLKEN0` reader
pub type R = crate::R<HFPERCLKEN0rs>;
///Register `HFPERCLKEN0` writer
pub type W = crate::W<HFPERCLKEN0rs>;
///Field `TIMER0` reader - Timer 0 Clock Enable
pub type Timer0R = crate::BitReader;
///Field `TIMER0` writer - Timer 0 Clock Enable
pub type Timer0W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIMER1` reader - Timer 1 Clock Enable
pub type Timer1R = crate::BitReader;
///Field `TIMER1` writer - Timer 1 Clock Enable
pub type Timer1W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
pub type Usart0R = crate::BitReader;
///Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
pub type Usart0W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
pub type Usart1R = crate::BitReader;
///Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
pub type Usart1W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ACMP0` reader - Analog Comparator 0 Clock Enable
pub type Acmp0R = crate::BitReader;
///Field `ACMP0` writer - Analog Comparator 0 Clock Enable
pub type Acmp0W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ACMP1` reader - Analog Comparator 1 Clock Enable
pub type Acmp1R = crate::BitReader;
///Field `ACMP1` writer - Analog Comparator 1 Clock Enable
pub type Acmp1W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CRYOTIMER` reader - CRYOTIMER Clock Enable
pub type CryotimerR = crate::BitReader;
///Field `CRYOTIMER` writer - CRYOTIMER Clock Enable
pub type CryotimerW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `I2C0` reader - I2C 0 Clock Enable
pub type I2c0R = crate::BitReader;
///Field `I2C0` writer - I2C 0 Clock Enable
pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable
pub type Adc0R = crate::BitReader;
///Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable
pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IDAC0` reader - Current Digital to Analog Converter 0 Clock Enable
pub type Idac0R = crate::BitReader;
///Field `IDAC0` writer - Current Digital to Analog Converter 0 Clock Enable
pub type Idac0W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - Timer 0 Clock Enable
    #[inline(always)]
    pub fn timer0(&self) -> Timer0R {
        Timer0R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Timer 1 Clock Enable
    #[inline(always)]
    pub fn timer1(&self) -> Timer1R {
        Timer1R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
    #[inline(always)]
    pub fn usart0(&self) -> Usart0R {
        Usart0R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
    #[inline(always)]
    pub fn usart1(&self) -> Usart1R {
        Usart1R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - Analog Comparator 0 Clock Enable
    #[inline(always)]
    pub fn acmp0(&self) -> Acmp0R {
        Acmp0R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - Analog Comparator 1 Clock Enable
    #[inline(always)]
    pub fn acmp1(&self) -> Acmp1R {
        Acmp1R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - CRYOTIMER Clock Enable
    #[inline(always)]
    pub fn cryotimer(&self) -> CryotimerR {
        CryotimerR::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - I2C 0 Clock Enable
    #[inline(always)]
    pub fn i2c0(&self) -> I2c0R {
        I2c0R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - Analog to Digital Converter 0 Clock Enable
    #[inline(always)]
    pub fn adc0(&self) -> Adc0R {
        Adc0R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - Current Digital to Analog Converter 0 Clock Enable
    #[inline(always)]
    pub fn idac0(&self) -> Idac0R {
        Idac0R::new(((self.bits >> 9) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HFPERCLKEN0")
            .field("timer0", &self.timer0())
            .field("timer1", &self.timer1())
            .field("usart0", &self.usart0())
            .field("usart1", &self.usart1())
            .field("acmp0", &self.acmp0())
            .field("acmp1", &self.acmp1())
            .field("cryotimer", &self.cryotimer())
            .field("i2c0", &self.i2c0())
            .field("adc0", &self.adc0())
            .field("idac0", &self.idac0())
            .finish()
    }
}
impl W {
    ///Bit 0 - Timer 0 Clock Enable
    #[inline(always)]
    pub fn timer0(&mut self) -> Timer0W<'_, HFPERCLKEN0rs> {
        Timer0W::new(self, 0)
    }
    ///Bit 1 - Timer 1 Clock Enable
    #[inline(always)]
    pub fn timer1(&mut self) -> Timer1W<'_, HFPERCLKEN0rs> {
        Timer1W::new(self, 1)
    }
    ///Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
    #[inline(always)]
    pub fn usart0(&mut self) -> Usart0W<'_, HFPERCLKEN0rs> {
        Usart0W::new(self, 2)
    }
    ///Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
    #[inline(always)]
    pub fn usart1(&mut self) -> Usart1W<'_, HFPERCLKEN0rs> {
        Usart1W::new(self, 3)
    }
    ///Bit 4 - Analog Comparator 0 Clock Enable
    #[inline(always)]
    pub fn acmp0(&mut self) -> Acmp0W<'_, HFPERCLKEN0rs> {
        Acmp0W::new(self, 4)
    }
    ///Bit 5 - Analog Comparator 1 Clock Enable
    #[inline(always)]
    pub fn acmp1(&mut self) -> Acmp1W<'_, HFPERCLKEN0rs> {
        Acmp1W::new(self, 5)
    }
    ///Bit 6 - CRYOTIMER Clock Enable
    #[inline(always)]
    pub fn cryotimer(&mut self) -> CryotimerW<'_, HFPERCLKEN0rs> {
        CryotimerW::new(self, 6)
    }
    ///Bit 7 - I2C 0 Clock Enable
    #[inline(always)]
    pub fn i2c0(&mut self) -> I2c0W<'_, HFPERCLKEN0rs> {
        I2c0W::new(self, 7)
    }
    ///Bit 8 - Analog to Digital Converter 0 Clock Enable
    #[inline(always)]
    pub fn adc0(&mut self) -> Adc0W<'_, HFPERCLKEN0rs> {
        Adc0W::new(self, 8)
    }
    ///Bit 9 - Current Digital to Analog Converter 0 Clock Enable
    #[inline(always)]
    pub fn idac0(&mut self) -> Idac0W<'_, HFPERCLKEN0rs> {
        Idac0W::new(self, 9)
    }
}
///High Frequency Peripheral Clock Enable Register 0
///
///You can [`read`](crate::Reg::read) this register and get [`hfperclken0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfperclken0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct HFPERCLKEN0rs;
impl crate::RegisterSpec for HFPERCLKEN0rs {
    type Ux = u32;
}
///`read()` method returns [`hfperclken0::R`](R) reader structure
impl crate::Readable for HFPERCLKEN0rs {}
///`write(|w| ..)` method takes [`hfperclken0::W`](W) writer structure
impl crate::Writable for HFPERCLKEN0rs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets HFPERCLKEN0 to value 0
impl crate::Resettable for HFPERCLKEN0rs {}