cyt4dn_b 0.0.1

Peripheral access crate for cyt4dn_b T2G family
Documentation 
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#[doc = "Register `TXEFC` reader"]
pub struct R(crate::R<TXEFC_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<TXEFC_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<TXEFC_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<TXEFC_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `TXEFC` writer"]
pub struct W(crate::W<TXEFC_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<TXEFC_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<TXEFC_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<TXEFC_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `EFSA` reader - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2)."]
pub type EFSA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EFSA` writer - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2)."]
pub type EFSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXEFC_SPEC, u16, u16, 14, O>;
#[doc = "Field `EFS` reader - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1"]
pub type EFS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EFS` writer - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1"]
pub type EFS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXEFC_SPEC, u8, u8, 6, O>;
#[doc = "Field `EFWM` reader - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled"]
pub type EFWM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EFWM` writer - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled"]
pub type EFWM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXEFC_SPEC, u8, u8, 6, O>;
impl R {
    #[doc = "Bits 2:15 - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2)."]
    #[inline(always)]
    pub fn efsa(&self) -> EFSA_R {
        EFSA_R::new(((self.bits >> 2) & 0x3fff) as u16)
    }
    #[doc = "Bits 16:21 - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1"]
    #[inline(always)]
    pub fn efs(&self) -> EFS_R {
        EFS_R::new(((self.bits >> 16) & 0x3f) as u8)
    }
    #[doc = "Bits 24:29 - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled"]
    #[inline(always)]
    pub fn efwm(&self) -> EFWM_R {
        EFWM_R::new(((self.bits >> 24) & 0x3f) as u8)
    }
}
impl W {
    #[doc = "Bits 2:15 - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2)."]
    #[inline(always)]
    #[must_use]
    pub fn efsa(&mut self) -> EFSA_W<2> {
        EFSA_W::new(self)
    }
    #[doc = "Bits 16:21 - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements 32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1"]
    #[inline(always)]
    #[must_use]
    pub fn efs(&mut self) -> EFS_W<16> {
        EFS_W::new(self)
    }
    #[doc = "Bits 24:29 - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) 32= Watermark interrupt disabled"]
    #[inline(always)]
    #[must_use]
    pub fn efwm(&mut self) -> EFWM_W<24> {
        EFWM_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Tx Event FIFO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"]
pub struct TXEFC_SPEC;
impl crate::RegisterSpec for TXEFC_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [txefc::R](R) reader structure"]
impl crate::Readable for TXEFC_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"]
impl crate::Writable for TXEFC_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TXEFC to value 0"]
impl crate::Resettable for TXEFC_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}