cortex-ar 0.3.0

CPU support for AArch32 Arm Cortex-R and Arm Cortex-A
Documentation 
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//! Code for managing HMPUIR (*Hyp MPU Type Register*)

use crate::register::{SysReg, SysRegRead};

/// HMPUIR (*Hyp MPU Type Register*)
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct Hmpuir {
    /// The number of EL2 MPU regions implemented
    #[bits(0..=7, r)]
    region: u8,
}

impl SysReg for Hmpuir {
    const CP: u32 = 15;
    const CRN: u32 = 0;
    const OP1: u32 = 4;
    const CRM: u32 = 0;
    const OP2: u32 = 4;
}
impl crate::register::SysRegRead for Hmpuir {}
impl Hmpuir {
    #[inline]
    /// Reads HMPUIR (*Hyp MPU Type Register*)
    pub fn read() -> Hmpuir {
        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
    }
}