cortex-ar 0.3.0

CPU support for AArch32 Arm Cortex-R and Arm Cortex-A
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

//! Code for managing CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)

use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};

/// CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct CnthpCval(pub u64);

impl SysReg64 for CnthpCval {
    const CP: u32 = 15;
    const OP1: u32 = 2;
    const CRM: u32 = 14;
}

impl SysRegRead64 for CnthpCval {}

impl CnthpCval {
    #[inline]
    /// Reads CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
    pub fn read() -> CnthpCval {
        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
    }
}

impl SysRegWrite64 for CnthpCval {}

impl CnthpCval {
    #[inline]
    /// Writes CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
    pub fn write(value: Self) {
        unsafe {
            <Self as SysRegWrite64>::write_raw(value.0);
        }
    }
}