consortium-pac-imx9 0.5.0

// Generated by scripts/pac/gen_interrupts.py -- do not edit by hand.
// Source: imx95 (cm7) interrupt table `MIMX9596`.
#![allow(non_camel_case_types)]

#[doc = "Interrupt lines of imx95 (cm7)."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Interrupt {
    #[doc = "CAN1 interrupt"]
    CAN1 = 8,
    #[doc = "CAN1 error interrupt"]
    CAN1_ERROR = 9,
    #[doc = "General Purpose Input/Output 1 interrupt 0"]
    GPIO1_0 = 10,
    #[doc = "General Purpose Input/Output 1 interrupt 1"]
    GPIO1_1 = 11,
    #[doc = "Improved Inter-Integrated Circuit 1 interrupt"]
    I3C1 = 12,
    #[doc = "Low Power Inter-Integrated Circuit module 1"]
    LPI2C1 = 13,
    #[doc = "Low Power Inter-Integrated Circuit module 2"]
    LPI2C2 = 14,
    #[doc = "Low Power Periodic Interrupt Timer 1"]
    LPIT1 = 15,
    #[doc = "Low Power Serial Peripheral Interface 1"]
    LPSPI1 = 16,
    #[doc = "Low Power Serial Peripheral Interface 2"]
    LPSPI2 = 17,
    #[doc = "Low Power Timer 1"]
    LPTMR1 = 18,
    #[doc = "Low Power UART 1"]
    LPUART1 = 19,
    #[doc = "Low Power UART 2"]
    LPUART2 = 20,
    #[doc = "V2X-FH MU APCH0 (APP0) interrupt"]
    V2X_FH_APCH0 = 27,
    #[doc = "V2X-FH MU APHSM1 (HSM1) interrupt"]
    V2X_FH_APHSM1 = 28,
    #[doc = "Timer PWM module 1"]
    TPM1 = 29,
    #[doc = "Timer PWM module 2"]
    TPM2 = 30,
    #[doc = "Watchdog 1 Interrupt"]
    WDOG1 = 31,
    #[doc = "Watchdog 2 Interrupt"]
    WDOG2 = 32,
    #[doc = "AONMIX TRDC transfer error interrupt"]
    TRDC_MGR_A = 33,
    #[doc = "Serial Audio Interface 1"]
    SAI1 = 34,
    #[doc = "CAN2 interrupt"]
    CAN2 = 38,
    #[doc = "CAN2 error interrupt"]
    CAN2_ERROR = 39,
    #[doc = "CAN3 interrupt"]
    CAN3 = 40,
    #[doc = "CAN3 error interrupt"]
    CAN3_ERROR = 41,
    #[doc = "CAN4 interrupt"]
    CAN4 = 42,
    #[doc = "CAN4 error interrupt"]
    CAN4_ERROR = 43,
    #[doc = "CAN5 interrupt"]
    CAN5 = 44,
    #[doc = "CAN5 error interrupt"]
    CAN5_ERROR = 45,
    #[doc = "Flexible IO 1 interrupt"]
    FLEXIO1 = 46,
    #[doc = "Flexible IO 2 interrupt"]
    FLEXIO2 = 47,
    #[doc = "FlexSPI controller interface interrupt 1"]
    FlexSPI1 = 48,
    #[doc = "General Purpose Input/Output 2 interrupt 0"]
    GPIO2_0 = 49,
    #[doc = "General Purpose Input/Output 2 interrupt 1"]
    GPIO2_1 = 50,
    #[doc = "General Purpose Input/Output 3 interrupt 0"]
    GPIO3_0 = 51,
    #[doc = "General Purpose Input/Output 3 interrupt 1"]
    GPIO3_1 = 52,
    #[doc = "General Purpose Input/Output 4 interrupt 0"]
    GPIO4_0 = 53,
    #[doc = "General Purpose Input/Output 4 interrupt 1"]
    GPIO4_1 = 54,
    #[doc = "General Purpose Input/Output 5 interrupt 0"]
    GPIO5_0 = 55,
    #[doc = "General Purpose Input/Output 5 interrupt 1"]
    GPIO5_1 = 56,
    #[doc = "Improved Inter-Integrated Circuit 2 interrupt"]
    I3C2 = 57,
    #[doc = "Low Power Inter-Integrated Circuit module 3"]
    LPI2C3 = 58,
    #[doc = "Low Power Inter-Integrated Circuit module 4"]
    LPI2C4 = 59,
    #[doc = "Low Power Periodic Interrupt Timer 2"]
    LPIT2 = 60,
    #[doc = "Low Power Serial Peripheral Interface 3"]
    LPSPI3 = 61,
    #[doc = "Low Power Serial Peripheral Interface 4"]
    LPSPI4 = 62,
    #[doc = "Low Power Timer 2"]
    LPTMR2 = 63,
    #[doc = "Low Power UART 3"]
    LPUART3 = 64,
    #[doc = "Low Power UART 4"]
    LPUART4 = 65,
    #[doc = "Low Power UART 5"]
    LPUART5 = 66,
    #[doc = "Low Power UART 6"]
    LPUART6 = 67,
    #[doc = "Low Power UART 7"]
    LPUART7 = 68,
    #[doc = "Low Power UART 8"]
    LPUART8 = 69,
    #[doc = "Timer PWM module 3"]
    TPM3 = 73,
    #[doc = "Timer PWM module 4"]
    TPM4 = 74,
    #[doc = "Timer PWM module 5"]
    TPM5 = 75,
    #[doc = "Timer PWM module 6"]
    TPM6 = 76,
    #[doc = "Watchdog 3 Interrupt"]
    WDOG3 = 77,
    #[doc = "Watchdog 4 Interrupt"]
    WDOG4 = 78,
    #[doc = "Watchdog 5 Interrupt"]
    WDOG5 = 79,
    #[doc = "ANAMIX TempSensor non-secure interrupt from Threshold 1"]
    TMPSNS1_THR1 = 80,
    #[doc = "ANAMIX TempSensor non-secure interrupt from Threshold 2"]
    TMPSNS1_THR2 = 81,
    #[doc = "ANAMIX TempSensor non-secure data ready interrupt"]
    TMPSNS1_DRDY = 82,
    #[doc = "CORTEXAMIX TempSensor non-secure interrupt from Threshold 1"]
    TMPSNS2_THR1 = 83,
    #[doc = "CORTEXAMIX TempSensor non-secure interrupt from Threshold 2"]
    TMPSNS2_THR2 = 84,
    #[doc = "CORTEXAMIX TempSensor non-secure data ready interrupt"]
    TMPSNS2_DRDY = 85,
    #[doc = "ultra Secure Digital Host Controller interrupt 1"]
    uSDHC1 = 86,
    #[doc = "ultra Secure Digital Host Controller interrupt 2"]
    uSDHC2 = 87,
    #[doc = "eDMA1 error interrupt"]
    DMA3_ERROR = 95,
    #[doc = "eDMA1 channel 0 interrupt"]
    DMA3_0 = 96,
    #[doc = "eDMA1 channel 1 interrupt"]
    DMA3_1 = 97,
    #[doc = "eDMA1 channel 2 interrupt"]
    DMA3_2 = 98,
    #[doc = "eDMA1 channel 3 interrupt"]
    DMA3_3 = 99,
    #[doc = "eDMA1 channel 4 interrupt"]
    DMA3_4 = 100,
    #[doc = "eDMA1 channel 5 interrupt"]
    DMA3_5 = 101,
    #[doc = "eDMA1 channel 6 interrupt"]
    DMA3_6 = 102,
    #[doc = "eDMA1 channel 7 interrupt"]
    DMA3_7 = 103,
    #[doc = "eDMA1 channel 8 interrupt"]
    DMA3_8 = 104,
    #[doc = "eDMA1 channel 9 interrupt"]
    DMA3_9 = 105,
    #[doc = "eDMA1 channel 10 interrupt"]
    DMA3_10 = 106,
    #[doc = "eDMA1 channel 11 interrupt"]
    DMA3_11 = 107,
    #[doc = "eDMA1 channel 12 interrupt"]
    DMA3_12 = 108,
    #[doc = "eDMA1 channel 13 interrupt"]
    DMA3_13 = 109,
    #[doc = "eDMA1 channel 14 interrupt"]
    DMA3_14 = 110,
    #[doc = "eDMA1 channel 15 interrupt"]
    DMA3_15 = 111,
    #[doc = "eDMA1 channel 16 interrupt"]
    DMA3_16 = 112,
    #[doc = "eDMA1 channel 17 interrupt"]
    DMA3_17 = 113,
    #[doc = "eDMA1 channel 18 interrupt"]
    DMA3_18 = 114,
    #[doc = "eDMA1 channel 19 interrupt"]
    DMA3_19 = 115,
    #[doc = "eDMA1 channel 20 interrupt"]
    DMA3_20 = 116,
    #[doc = "eDMA1 channel 21 interrupt"]
    DMA3_21 = 117,
    #[doc = "eDMA1 channel 22 interrupt"]
    DMA3_22 = 118,
    #[doc = "eDMA1 channel 23 interrupt"]
    DMA3_23 = 119,
    #[doc = "eDMA1 channel 24 interrupt"]
    DMA3_24 = 120,
    #[doc = "eDMA1 channel 25 interrupt"]
    DMA3_25 = 121,
    #[doc = "eDMA1 channel 26 interrupt"]
    DMA3_26 = 122,
    #[doc = "eDMA1 channel 27 interrupt"]
    DMA3_27 = 123,
    #[doc = "eDMA1 channel 28 interrupt"]
    DMA3_28 = 124,
    #[doc = "eDMA1 channel 29 interrupt"]
    DMA3_29 = 125,
    #[doc = "eDMA1 channel 30 interrupt"]
    DMA3_30 = 126,
    #[doc = "eDMA2 error interrupt"]
    DMA5_2_ERROR = 127,
    #[doc = "eDMA2 channel 0/1 interrupt"]
    DMA5_2_0_1 = 128,
    #[doc = "eDMA2 channel 2/3 interrupt"]
    DMA5_2_2_3 = 129,
    #[doc = "eDMA2 channel 4/5 interrupt"]
    DMA5_2_4_5 = 130,
    #[doc = "eDMA2 channel 6/7 interrupt"]
    DMA5_2_6_7 = 131,
    #[doc = "eDMA2 channel 8/9 interrupt"]
    DMA5_2_8_9 = 132,
    #[doc = "eDMA2 channel 10/11 interrupt"]
    DMA5_2_10_11 = 133,
    #[doc = "eDMA2 channel 12/13 interrupt"]
    DMA5_2_12_13 = 134,
    #[doc = "eDMA2 channel 14/15 interrupt"]
    DMA5_2_14_15 = 135,
    #[doc = "eDMA2 channel 16/17 interrupt"]
    DMA5_2_16_17 = 136,
    #[doc = "eDMA2 channel 18/19 interrupt"]
    DMA5_2_18_19 = 137,
    #[doc = "eDMA2 channel 20/21 interrupt"]
    DMA5_2_20_21 = 138,
    #[doc = "eDMA2 channel 22/23 interrupt"]
    DMA5_2_22_23 = 139,
    #[doc = "eDMA2 channel 24/25 interrupt"]
    DMA5_2_24_25 = 140,
    #[doc = "eDMA2 channel 26/27 interrupt"]
    DMA5_2_26_27 = 141,
    #[doc = "eDMA2 channel 28/29 interrupt"]
    DMA5_2_28_29 = 142,
    #[doc = "eDMA2 channel 30/31 interrupt"]
    DMA5_2_30_31 = 143,
    #[doc = "eDMA2 channel 32/33 interrupt"]
    DMA5_2_32_33 = 144,
    #[doc = "eDMA2 channel 34/35 interrupt"]
    DMA5_2_34_35 = 145,
    #[doc = "eDMA2 channel 36/37 interrupt"]
    DMA5_2_36_37 = 146,
    #[doc = "eDMA2 channel 38/39 interrupt"]
    DMA5_2_38_39 = 147,
    #[doc = "eDMA2 channel 40/41 interrupt"]
    DMA5_2_40_41 = 148,
    #[doc = "eDMA2 channel 42/43 interrupt"]
    DMA5_2_42_43 = 149,
    #[doc = "eDMA2 channel 44/45 interrupt"]
    DMA5_2_44_45 = 150,
    #[doc = "eDMA2 channel 46/47 interrupt"]
    DMA5_2_46_47 = 151,
    #[doc = "eDMA2 channel 48/49 interrupt"]
    DMA5_2_48_49 = 152,
    #[doc = "eDMA2 channel 50/51 interrupt"]
    DMA5_2_50_51 = 153,
    #[doc = "eDMA2 channel 52/53 interrupt"]
    DMA5_2_52_53 = 154,
    #[doc = "eDMA2 channel 54/55 interrupt"]
    DMA5_2_54_55 = 155,
    #[doc = "eDMA2 channel 56/57 interrupt"]
    DMA5_2_56_57 = 156,
    #[doc = "eDMA2 channel 58/59 interrupt"]
    DMA5_2_58_59 = 157,
    #[doc = "eDMA2 channel 60/61 interrupt"]
    DMA5_2_60_61 = 158,
    #[doc = "eDMA2 channel 62/63 interrupt"]
    DMA5_2_62_63 = 159,
    #[doc = "Serial Audio Interface 2"]
    SAI2 = 169,
    #[doc = "Serial Audio Interface 3"]
    SAI3 = 170,
    #[doc = "Serial Audio Interface 4"]
    SAI4 = 171,
    #[doc = "Serial Audio Interface 5"]
    SAI5 = 172,
    #[doc = "USB-1 Interrupt"]
    USB1 = 175,
    #[doc = "USB-2 Interrupt"]
    USB2 = 176,
    #[doc = "Low Power Serial Peripheral Interface 5"]
    LPSPI5 = 177,
    #[doc = "Low Power Serial Peripheral Interface 6"]
    LPSPI6 = 178,
    #[doc = "Low Power Serial Peripheral Interface 7"]
    LPSPI7 = 179,
    #[doc = "Low Power Serial Peripheral Interface 8"]
    LPSPI8 = 180,
    #[doc = "Low Power Inter-Integrated Circuit module 5"]
    LPI2C5 = 181,
    #[doc = "Low Power Inter-Integrated Circuit module 6"]
    LPI2C6 = 182,
    #[doc = "Low Power Inter-Integrated Circuit module 7"]
    LPI2C7 = 183,
    #[doc = "Low Power Inter-Integrated Circuit module 8"]
    LPI2C8 = 184,
    #[doc = "PDM interrupt"]
    PDM_HWVAD_ERROR = 185,
    #[doc = "PDM interrupt"]
    PDM_HWVAD_EVENT = 186,
    #[doc = "PDM interrupt"]
    PDM_ERROR = 187,
    #[doc = "PDM interrupt"]
    PDM_EVENT = 188,
    #[doc = "ultra Secure Digital Host Controller interrupt 3"]
    uSDHC3 = 191,
    #[doc = "ADC interrupt"]
    ADC_ER = 199,
    #[doc = "ADC interrupt"]
    ADC_WD = 200,
    #[doc = "ADC interrupt"]
    ADC_EOC = 201,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA"]
    MU5_A = 205,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA"]
    MU6_A = 206,
    #[doc = "WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB"]
    MU7_B = 207,
    #[doc = "WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB"]
    MU8_B = 208,
    #[doc = "DISPLAYMIX IRQSTEER 0"]
    DISP_IRQSTEER0 = 214,
    #[doc = "DISPLAYMIX IRQSTEER 1"]
    DISP_IRQSTEER1 = 215,
    #[doc = "DISPLAYMIX IRQSTEER 2"]
    DISP_IRQSTEER2 = 216,
    #[doc = "DISPLAYMIX IRQSTEER 3"]
    DISP_IRQSTEER3 = 217,
    #[doc = "DISPLAYMIX IRQSTEER 4"]
    DISP_IRQSTEER4 = 218,
    #[doc = "DISPLAYMIX IRQSTEER 7"]
    DISP_IRQSTEER7 = 219,
    #[doc = "CAMERAMIX ISI interrupt Channel 0"]
    ISI = 221,
    #[doc = "ISP Processing Interrupt - Context 0"]
    ISP = 222,
    #[doc = "IRQSTEER0 interrupt"]
    IRQSTEER_0 = 224,
    #[doc = "IRQSTEER1 interrupt"]
    IRQSTEER_1 = 225,
    #[doc = "IRQSTEER2 interrupt"]
    IRQSTEER_2 = 226,
    #[doc = "IRQSTEER3 interrupt"]
    IRQSTEER_3 = 227,
    #[doc = "IRQSTEER4 interrupt"]
    IRQSTEER_4 = 228,
    #[doc = "IRQSTEER5 interrupt"]
    IRQSTEER_5 = 229,
    #[doc = "IRQSTEER6 interrupt"]
    IRQSTEER_6 = 230,
    #[doc = "IRQSTEER7 interrupt"]
    IRQSTEER_7 = 231,
    #[doc = "IRQSTEER8 interrupt"]
    IRQSTEER_8 = 232,
    #[doc = "IRQSTEER9 interrupt"]
    IRQSTEER_9 = 233,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA"]
    MU1_A = 234,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB"]
    MU1_B = 235,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA"]
    MU2_A = 236,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB"]
    MU2_B = 237,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA"]
    MU3_A = 238,
    #[doc = "AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB"]
    MU3_B = 239,
}

// SAFETY: each variant carries the external interrupt number defined by the
// chip's vendor headers, so `number` returns a valid NVIC line.
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}

// `#[interrupt]` handler support. The attribute macro (macro namespace)
// and the `Interrupt` alias (type namespace) share the name `interrupt`,
// so the macro's generated `interrupt::NAME;` existence check resolves.
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;

#[cfg(feature = "rt")]
#[doc(hidden)]
#[allow(dead_code)]
pub union Vector {
    handler: unsafe extern "C" fn(),
    reserved: usize,
}

#[cfg(feature = "rt")]
unsafe extern "C" {
    fn CAN1();
    fn CAN1_ERROR();
    fn GPIO1_0();
    fn GPIO1_1();
    fn I3C1();
    fn LPI2C1();
    fn LPI2C2();
    fn LPIT1();
    fn LPSPI1();
    fn LPSPI2();
    fn LPTMR1();
    fn LPUART1();
    fn LPUART2();
    fn V2X_FH_APCH0();
    fn V2X_FH_APHSM1();
    fn TPM1();
    fn TPM2();
    fn WDOG1();
    fn WDOG2();
    fn TRDC_MGR_A();
    fn SAI1();
    fn CAN2();
    fn CAN2_ERROR();
    fn CAN3();
    fn CAN3_ERROR();
    fn CAN4();
    fn CAN4_ERROR();
    fn CAN5();
    fn CAN5_ERROR();
    fn FLEXIO1();
    fn FLEXIO2();
    fn FlexSPI1();
    fn GPIO2_0();
    fn GPIO2_1();
    fn GPIO3_0();
    fn GPIO3_1();
    fn GPIO4_0();
    fn GPIO4_1();
    fn GPIO5_0();
    fn GPIO5_1();
    fn I3C2();
    fn LPI2C3();
    fn LPI2C4();
    fn LPIT2();
    fn LPSPI3();
    fn LPSPI4();
    fn LPTMR2();
    fn LPUART3();
    fn LPUART4();
    fn LPUART5();
    fn LPUART6();
    fn LPUART7();
    fn LPUART8();
    fn TPM3();
    fn TPM4();
    fn TPM5();
    fn TPM6();
    fn WDOG3();
    fn WDOG4();
    fn WDOG5();
    fn TMPSNS1_THR1();
    fn TMPSNS1_THR2();
    fn TMPSNS1_DRDY();
    fn TMPSNS2_THR1();
    fn TMPSNS2_THR2();
    fn TMPSNS2_DRDY();
    fn uSDHC1();
    fn uSDHC2();
    fn DMA3_ERROR();
    fn DMA3_0();
    fn DMA3_1();
    fn DMA3_2();
    fn DMA3_3();
    fn DMA3_4();
    fn DMA3_5();
    fn DMA3_6();
    fn DMA3_7();
    fn DMA3_8();
    fn DMA3_9();
    fn DMA3_10();
    fn DMA3_11();
    fn DMA3_12();
    fn DMA3_13();
    fn DMA3_14();
    fn DMA3_15();
    fn DMA3_16();
    fn DMA3_17();
    fn DMA3_18();
    fn DMA3_19();
    fn DMA3_20();
    fn DMA3_21();
    fn DMA3_22();
    fn DMA3_23();
    fn DMA3_24();
    fn DMA3_25();
    fn DMA3_26();
    fn DMA3_27();
    fn DMA3_28();
    fn DMA3_29();
    fn DMA3_30();
    fn DMA5_2_ERROR();
    fn DMA5_2_0_1();
    fn DMA5_2_2_3();
    fn DMA5_2_4_5();
    fn DMA5_2_6_7();
    fn DMA5_2_8_9();
    fn DMA5_2_10_11();
    fn DMA5_2_12_13();
    fn DMA5_2_14_15();
    fn DMA5_2_16_17();
    fn DMA5_2_18_19();
    fn DMA5_2_20_21();
    fn DMA5_2_22_23();
    fn DMA5_2_24_25();
    fn DMA5_2_26_27();
    fn DMA5_2_28_29();
    fn DMA5_2_30_31();
    fn DMA5_2_32_33();
    fn DMA5_2_34_35();
    fn DMA5_2_36_37();
    fn DMA5_2_38_39();
    fn DMA5_2_40_41();
    fn DMA5_2_42_43();
    fn DMA5_2_44_45();
    fn DMA5_2_46_47();
    fn DMA5_2_48_49();
    fn DMA5_2_50_51();
    fn DMA5_2_52_53();
    fn DMA5_2_54_55();
    fn DMA5_2_56_57();
    fn DMA5_2_58_59();
    fn DMA5_2_60_61();
    fn DMA5_2_62_63();
    fn SAI2();
    fn SAI3();
    fn SAI4();
    fn SAI5();
    fn USB1();
    fn USB2();
    fn LPSPI5();
    fn LPSPI6();
    fn LPSPI7();
    fn LPSPI8();
    fn LPI2C5();
    fn LPI2C6();
    fn LPI2C7();
    fn LPI2C8();
    fn PDM_HWVAD_ERROR();
    fn PDM_HWVAD_EVENT();
    fn PDM_ERROR();
    fn PDM_EVENT();
    fn uSDHC3();
    fn ADC_ER();
    fn ADC_WD();
    fn ADC_EOC();
    fn MU5_A();
    fn MU6_A();
    fn MU7_B();
    fn MU8_B();
    fn DISP_IRQSTEER0();
    fn DISP_IRQSTEER1();
    fn DISP_IRQSTEER2();
    fn DISP_IRQSTEER3();
    fn DISP_IRQSTEER4();
    fn DISP_IRQSTEER7();
    fn ISI();
    fn ISP();
    fn IRQSTEER_0();
    fn IRQSTEER_1();
    fn IRQSTEER_2();
    fn IRQSTEER_3();
    fn IRQSTEER_4();
    fn IRQSTEER_5();
    fn IRQSTEER_6();
    fn IRQSTEER_7();
    fn IRQSTEER_8();
    fn IRQSTEER_9();
    fn MU1_A();
    fn MU1_B();
    fn MU2_A();
    fn MU2_B();
    fn MU3_A();
    fn MU3_B();
}

#[doc = "Device-specific interrupt portion of the vector table for imx95 (cm7)."]
#[cfg(feature = "rt")]
#[doc(hidden)]
#[unsafe(link_section = ".vector_table.interrupts")]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [Vector; 240] = [
    Vector { reserved: 0 },   // 0: reserved
    Vector { reserved: 0 },   // 1: reserved
    Vector { reserved: 0 },   // 2: reserved
    Vector { reserved: 0 },   // 3: reserved
    Vector { reserved: 0 },   // 4: reserved
    Vector { reserved: 0 },   // 5: reserved
    Vector { reserved: 0 },   // 6: reserved
    Vector { reserved: 0 },   // 7: reserved
    Vector { handler: CAN1 }, // 8: CAN1
    Vector {
        handler: CAN1_ERROR,
    }, // 9: CAN1_ERROR
    Vector { handler: GPIO1_0 }, // 10: GPIO1_0
    Vector { handler: GPIO1_1 }, // 11: GPIO1_1
    Vector { handler: I3C1 }, // 12: I3C1
    Vector { handler: LPI2C1 }, // 13: LPI2C1
    Vector { handler: LPI2C2 }, // 14: LPI2C2
    Vector { handler: LPIT1 }, // 15: LPIT1
    Vector { handler: LPSPI1 }, // 16: LPSPI1
    Vector { handler: LPSPI2 }, // 17: LPSPI2
    Vector { handler: LPTMR1 }, // 18: LPTMR1
    Vector { handler: LPUART1 }, // 19: LPUART1
    Vector { handler: LPUART2 }, // 20: LPUART2
    Vector { reserved: 0 },   // 21: reserved
    Vector { reserved: 0 },   // 22: reserved
    Vector { reserved: 0 },   // 23: reserved
    Vector { reserved: 0 },   // 24: reserved
    Vector { reserved: 0 },   // 25: reserved
    Vector { reserved: 0 },   // 26: reserved
    Vector {
        handler: V2X_FH_APCH0,
    }, // 27: V2X_FH_APCH0
    Vector {
        handler: V2X_FH_APHSM1,
    }, // 28: V2X_FH_APHSM1
    Vector { handler: TPM1 }, // 29: TPM1
    Vector { handler: TPM2 }, // 30: TPM2
    Vector { handler: WDOG1 }, // 31: WDOG1
    Vector { handler: WDOG2 }, // 32: WDOG2
    Vector {
        handler: TRDC_MGR_A,
    }, // 33: TRDC_MGR_A
    Vector { handler: SAI1 }, // 34: SAI1
    Vector { reserved: 0 },   // 35: reserved
    Vector { reserved: 0 },   // 36: reserved
    Vector { reserved: 0 },   // 37: reserved
    Vector { handler: CAN2 }, // 38: CAN2
    Vector {
        handler: CAN2_ERROR,
    }, // 39: CAN2_ERROR
    Vector { handler: CAN3 }, // 40: CAN3
    Vector {
        handler: CAN3_ERROR,
    }, // 41: CAN3_ERROR
    Vector { handler: CAN4 }, // 42: CAN4
    Vector {
        handler: CAN4_ERROR,
    }, // 43: CAN4_ERROR
    Vector { handler: CAN5 }, // 44: CAN5
    Vector {
        handler: CAN5_ERROR,
    }, // 45: CAN5_ERROR
    Vector { handler: FLEXIO1 }, // 46: FLEXIO1
    Vector { handler: FLEXIO2 }, // 47: FLEXIO2
    Vector { handler: FlexSPI1 }, // 48: FlexSPI1
    Vector { handler: GPIO2_0 }, // 49: GPIO2_0
    Vector { handler: GPIO2_1 }, // 50: GPIO2_1
    Vector { handler: GPIO3_0 }, // 51: GPIO3_0
    Vector { handler: GPIO3_1 }, // 52: GPIO3_1
    Vector { handler: GPIO4_0 }, // 53: GPIO4_0
    Vector { handler: GPIO4_1 }, // 54: GPIO4_1
    Vector { handler: GPIO5_0 }, // 55: GPIO5_0
    Vector { handler: GPIO5_1 }, // 56: GPIO5_1
    Vector { handler: I3C2 }, // 57: I3C2
    Vector { handler: LPI2C3 }, // 58: LPI2C3
    Vector { handler: LPI2C4 }, // 59: LPI2C4
    Vector { handler: LPIT2 }, // 60: LPIT2
    Vector { handler: LPSPI3 }, // 61: LPSPI3
    Vector { handler: LPSPI4 }, // 62: LPSPI4
    Vector { handler: LPTMR2 }, // 63: LPTMR2
    Vector { handler: LPUART3 }, // 64: LPUART3
    Vector { handler: LPUART4 }, // 65: LPUART4
    Vector { handler: LPUART5 }, // 66: LPUART5
    Vector { handler: LPUART6 }, // 67: LPUART6
    Vector { handler: LPUART7 }, // 68: LPUART7
    Vector { handler: LPUART8 }, // 69: LPUART8
    Vector { reserved: 0 },   // 70: reserved
    Vector { reserved: 0 },   // 71: reserved
    Vector { reserved: 0 },   // 72: reserved
    Vector { handler: TPM3 }, // 73: TPM3
    Vector { handler: TPM4 }, // 74: TPM4
    Vector { handler: TPM5 }, // 75: TPM5
    Vector { handler: TPM6 }, // 76: TPM6
    Vector { handler: WDOG3 }, // 77: WDOG3
    Vector { handler: WDOG4 }, // 78: WDOG4
    Vector { handler: WDOG5 }, // 79: WDOG5
    Vector {
        handler: TMPSNS1_THR1,
    }, // 80: TMPSNS1_THR1
    Vector {
        handler: TMPSNS1_THR2,
    }, // 81: TMPSNS1_THR2
    Vector {
        handler: TMPSNS1_DRDY,
    }, // 82: TMPSNS1_DRDY
    Vector {
        handler: TMPSNS2_THR1,
    }, // 83: TMPSNS2_THR1
    Vector {
        handler: TMPSNS2_THR2,
    }, // 84: TMPSNS2_THR2
    Vector {
        handler: TMPSNS2_DRDY,
    }, // 85: TMPSNS2_DRDY
    Vector { handler: uSDHC1 }, // 86: uSDHC1
    Vector { handler: uSDHC2 }, // 87: uSDHC2
    Vector { reserved: 0 },   // 88: reserved
    Vector { reserved: 0 },   // 89: reserved
    Vector { reserved: 0 },   // 90: reserved
    Vector { reserved: 0 },   // 91: reserved
    Vector { reserved: 0 },   // 92: reserved
    Vector { reserved: 0 },   // 93: reserved
    Vector { reserved: 0 },   // 94: reserved
    Vector {
        handler: DMA3_ERROR,
    }, // 95: DMA3_ERROR
    Vector { handler: DMA3_0 }, // 96: DMA3_0
    Vector { handler: DMA3_1 }, // 97: DMA3_1
    Vector { handler: DMA3_2 }, // 98: DMA3_2
    Vector { handler: DMA3_3 }, // 99: DMA3_3
    Vector { handler: DMA3_4 }, // 100: DMA3_4
    Vector { handler: DMA3_5 }, // 101: DMA3_5
    Vector { handler: DMA3_6 }, // 102: DMA3_6
    Vector { handler: DMA3_7 }, // 103: DMA3_7
    Vector { handler: DMA3_8 }, // 104: DMA3_8
    Vector { handler: DMA3_9 }, // 105: DMA3_9
    Vector { handler: DMA3_10 }, // 106: DMA3_10
    Vector { handler: DMA3_11 }, // 107: DMA3_11
    Vector { handler: DMA3_12 }, // 108: DMA3_12
    Vector { handler: DMA3_13 }, // 109: DMA3_13
    Vector { handler: DMA3_14 }, // 110: DMA3_14
    Vector { handler: DMA3_15 }, // 111: DMA3_15
    Vector { handler: DMA3_16 }, // 112: DMA3_16
    Vector { handler: DMA3_17 }, // 113: DMA3_17
    Vector { handler: DMA3_18 }, // 114: DMA3_18
    Vector { handler: DMA3_19 }, // 115: DMA3_19
    Vector { handler: DMA3_20 }, // 116: DMA3_20
    Vector { handler: DMA3_21 }, // 117: DMA3_21
    Vector { handler: DMA3_22 }, // 118: DMA3_22
    Vector { handler: DMA3_23 }, // 119: DMA3_23
    Vector { handler: DMA3_24 }, // 120: DMA3_24
    Vector { handler: DMA3_25 }, // 121: DMA3_25
    Vector { handler: DMA3_26 }, // 122: DMA3_26
    Vector { handler: DMA3_27 }, // 123: DMA3_27
    Vector { handler: DMA3_28 }, // 124: DMA3_28
    Vector { handler: DMA3_29 }, // 125: DMA3_29
    Vector { handler: DMA3_30 }, // 126: DMA3_30
    Vector {
        handler: DMA5_2_ERROR,
    }, // 127: DMA5_2_ERROR
    Vector {
        handler: DMA5_2_0_1,
    }, // 128: DMA5_2_0_1
    Vector {
        handler: DMA5_2_2_3,
    }, // 129: DMA5_2_2_3
    Vector {
        handler: DMA5_2_4_5,
    }, // 130: DMA5_2_4_5
    Vector {
        handler: DMA5_2_6_7,
    }, // 131: DMA5_2_6_7
    Vector {
        handler: DMA5_2_8_9,
    }, // 132: DMA5_2_8_9
    Vector {
        handler: DMA5_2_10_11,
    }, // 133: DMA5_2_10_11
    Vector {
        handler: DMA5_2_12_13,
    }, // 134: DMA5_2_12_13
    Vector {
        handler: DMA5_2_14_15,
    }, // 135: DMA5_2_14_15
    Vector {
        handler: DMA5_2_16_17,
    }, // 136: DMA5_2_16_17
    Vector {
        handler: DMA5_2_18_19,
    }, // 137: DMA5_2_18_19
    Vector {
        handler: DMA5_2_20_21,
    }, // 138: DMA5_2_20_21
    Vector {
        handler: DMA5_2_22_23,
    }, // 139: DMA5_2_22_23
    Vector {
        handler: DMA5_2_24_25,
    }, // 140: DMA5_2_24_25
    Vector {
        handler: DMA5_2_26_27,
    }, // 141: DMA5_2_26_27
    Vector {
        handler: DMA5_2_28_29,
    }, // 142: DMA5_2_28_29
    Vector {
        handler: DMA5_2_30_31,
    }, // 143: DMA5_2_30_31
    Vector {
        handler: DMA5_2_32_33,
    }, // 144: DMA5_2_32_33
    Vector {
        handler: DMA5_2_34_35,
    }, // 145: DMA5_2_34_35
    Vector {
        handler: DMA5_2_36_37,
    }, // 146: DMA5_2_36_37
    Vector {
        handler: DMA5_2_38_39,
    }, // 147: DMA5_2_38_39
    Vector {
        handler: DMA5_2_40_41,
    }, // 148: DMA5_2_40_41
    Vector {
        handler: DMA5_2_42_43,
    }, // 149: DMA5_2_42_43
    Vector {
        handler: DMA5_2_44_45,
    }, // 150: DMA5_2_44_45
    Vector {
        handler: DMA5_2_46_47,
    }, // 151: DMA5_2_46_47
    Vector {
        handler: DMA5_2_48_49,
    }, // 152: DMA5_2_48_49
    Vector {
        handler: DMA5_2_50_51,
    }, // 153: DMA5_2_50_51
    Vector {
        handler: DMA5_2_52_53,
    }, // 154: DMA5_2_52_53
    Vector {
        handler: DMA5_2_54_55,
    }, // 155: DMA5_2_54_55
    Vector {
        handler: DMA5_2_56_57,
    }, // 156: DMA5_2_56_57
    Vector {
        handler: DMA5_2_58_59,
    }, // 157: DMA5_2_58_59
    Vector {
        handler: DMA5_2_60_61,
    }, // 158: DMA5_2_60_61
    Vector {
        handler: DMA5_2_62_63,
    }, // 159: DMA5_2_62_63
    Vector { reserved: 0 },   // 160: reserved
    Vector { reserved: 0 },   // 161: reserved
    Vector { reserved: 0 },   // 162: reserved
    Vector { reserved: 0 },   // 163: reserved
    Vector { reserved: 0 },   // 164: reserved
    Vector { reserved: 0 },   // 165: reserved
    Vector { reserved: 0 },   // 166: reserved
    Vector { reserved: 0 },   // 167: reserved
    Vector { reserved: 0 },   // 168: reserved
    Vector { handler: SAI2 }, // 169: SAI2
    Vector { handler: SAI3 }, // 170: SAI3
    Vector { handler: SAI4 }, // 171: SAI4
    Vector { handler: SAI5 }, // 172: SAI5
    Vector { reserved: 0 },   // 173: reserved
    Vector { reserved: 0 },   // 174: reserved
    Vector { handler: USB1 }, // 175: USB1
    Vector { handler: USB2 }, // 176: USB2
    Vector { handler: LPSPI5 }, // 177: LPSPI5
    Vector { handler: LPSPI6 }, // 178: LPSPI6
    Vector { handler: LPSPI7 }, // 179: LPSPI7
    Vector { handler: LPSPI8 }, // 180: LPSPI8
    Vector { handler: LPI2C5 }, // 181: LPI2C5
    Vector { handler: LPI2C6 }, // 182: LPI2C6
    Vector { handler: LPI2C7 }, // 183: LPI2C7
    Vector { handler: LPI2C8 }, // 184: LPI2C8
    Vector {
        handler: PDM_HWVAD_ERROR,
    }, // 185: PDM_HWVAD_ERROR
    Vector {
        handler: PDM_HWVAD_EVENT,
    }, // 186: PDM_HWVAD_EVENT
    Vector { handler: PDM_ERROR }, // 187: PDM_ERROR
    Vector { handler: PDM_EVENT }, // 188: PDM_EVENT
    Vector { reserved: 0 },   // 189: reserved
    Vector { reserved: 0 },   // 190: reserved
    Vector { handler: uSDHC3 }, // 191: uSDHC3
    Vector { reserved: 0 },   // 192: reserved
    Vector { reserved: 0 },   // 193: reserved
    Vector { reserved: 0 },   // 194: reserved
    Vector { reserved: 0 },   // 195: reserved
    Vector { reserved: 0 },   // 196: reserved
    Vector { reserved: 0 },   // 197: reserved
    Vector { reserved: 0 },   // 198: reserved
    Vector { handler: ADC_ER }, // 199: ADC_ER
    Vector { handler: ADC_WD }, // 200: ADC_WD
    Vector { handler: ADC_EOC }, // 201: ADC_EOC
    Vector { reserved: 0 },   // 202: reserved
    Vector { reserved: 0 },   // 203: reserved
    Vector { reserved: 0 },   // 204: reserved
    Vector { handler: MU5_A }, // 205: MU5_A
    Vector { handler: MU6_A }, // 206: MU6_A
    Vector { handler: MU7_B }, // 207: MU7_B
    Vector { handler: MU8_B }, // 208: MU8_B
    Vector { reserved: 0 },   // 209: reserved
    Vector { reserved: 0 },   // 210: reserved
    Vector { reserved: 0 },   // 211: reserved
    Vector { reserved: 0 },   // 212: reserved
    Vector { reserved: 0 },   // 213: reserved
    Vector {
        handler: DISP_IRQSTEER0,
    }, // 214: DISP_IRQSTEER0
    Vector {
        handler: DISP_IRQSTEER1,
    }, // 215: DISP_IRQSTEER1
    Vector {
        handler: DISP_IRQSTEER2,
    }, // 216: DISP_IRQSTEER2
    Vector {
        handler: DISP_IRQSTEER3,
    }, // 217: DISP_IRQSTEER3
    Vector {
        handler: DISP_IRQSTEER4,
    }, // 218: DISP_IRQSTEER4
    Vector {
        handler: DISP_IRQSTEER7,
    }, // 219: DISP_IRQSTEER7
    Vector { reserved: 0 },   // 220: reserved
    Vector { handler: ISI },  // 221: ISI
    Vector { handler: ISP },  // 222: ISP
    Vector { reserved: 0 },   // 223: reserved
    Vector {
        handler: IRQSTEER_0,
    }, // 224: IRQSTEER_0
    Vector {
        handler: IRQSTEER_1,
    }, // 225: IRQSTEER_1
    Vector {
        handler: IRQSTEER_2,
    }, // 226: IRQSTEER_2
    Vector {
        handler: IRQSTEER_3,
    }, // 227: IRQSTEER_3
    Vector {
        handler: IRQSTEER_4,
    }, // 228: IRQSTEER_4
    Vector {
        handler: IRQSTEER_5,
    }, // 229: IRQSTEER_5
    Vector {
        handler: IRQSTEER_6,
    }, // 230: IRQSTEER_6
    Vector {
        handler: IRQSTEER_7,
    }, // 231: IRQSTEER_7
    Vector {
        handler: IRQSTEER_8,
    }, // 232: IRQSTEER_8
    Vector {
        handler: IRQSTEER_9,
    }, // 233: IRQSTEER_9
    Vector { handler: MU1_A }, // 234: MU1_A
    Vector { handler: MU1_B }, // 235: MU1_B
    Vector { handler: MU2_A }, // 236: MU2_A
    Vector { handler: MU2_B }, // 237: MU2_B
    Vector { handler: MU3_A }, // 238: MU3_A
    Vector { handler: MU3_B }, // 239: MU3_B
];