consortium-pac-imx9 0.5.0

// Generated by scripts/pac/gen_interrupts.py -- do not edit by hand.
// Source: imx93 (cm33) interrupt table `MIMX9352`.
#![allow(non_camel_case_types)]

#[doc = "Interrupt lines of imx93 (cm33)."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Interrupt {
    #[doc = "DAP interrupt"]
    DAP = 1,
    #[doc = "CTI trigger outputs from CM33 platform"]
    CTI_CM33 = 3,
    #[doc = "CTI trigger outputs from CA55 platform"]
    CTI_CA55 = 4,
    #[doc = "Performance Unit Interrupts from CA55 platform"]
    PMU = 5,
    #[doc = "ECC error from CA55 platform cache"]
    CACHE_ECC_ERR = 6,
    #[doc = "1-bit or 2-bit ECC or Parity error from CA55 platform cache"]
    CACHE_ECC_PARITY_ERR = 7,
    #[doc = "CAN1 interrupt"]
    CAN1 = 8,
    #[doc = "CAN1 error interrupt"]
    CAN1_ERROR = 9,
    #[doc = "General Purpose Input/Output 1 interrupt 0"]
    GPIO1_0 = 10,
    #[doc = "General Purpose Input/Output 1 interrupt 1"]
    GPIO1_1 = 11,
    #[doc = "Improved Inter-Integrated Circuit 1 interrupt"]
    I3C1 = 12,
    #[doc = "Low Power Inter-Integrated Circuit module 1"]
    LPI2C1 = 13,
    #[doc = "Low Power Inter-Integrated Circuit module 2"]
    LPI2C2 = 14,
    #[doc = "Low Power Periodic Interrupt Timer 1"]
    LPIT1 = 15,
    #[doc = "Low Power Serial Peripheral Interface 1"]
    LPSPI1 = 16,
    #[doc = "Low Power Serial Peripheral Interface 2"]
    LPSPI2 = 17,
    #[doc = "Low Power Timer 1"]
    LPTMR1 = 18,
    #[doc = "Low Power UART 1"]
    LPUART1 = 19,
    #[doc = "Low Power UART 2"]
    LPUART2 = 20,
    #[doc = "Messaging Unit 1 - Side A (to communicate with M7 core)"]
    MU1_A = 21,
    #[doc = "Messaging Unit 1 - Side B (to communicate with M33 core)"]
    MU1_B = 22,
    #[doc = "Messaging Unit 2 - Side A (to communicate with M7 core)"]
    MU2_A = 23,
    #[doc = "Messaging Unit 2 - Side B (to communicate with A55 core)"]
    MU2_B = 24,
    #[doc = "Edgelock Trust MUA RX full interrupt"]
    EDGELOCK_TRUST_MUA_RX = 28,
    #[doc = "Edgelock Trust MUA TX empty interrupt"]
    EDGELOCK_TRUST_MUA_TX = 29,
    #[doc = "Edgelock Apps Core MUA RX full interrupt"]
    EDGELOCK_APP_MUA_RX = 30,
    #[doc = "Edgelock Apps Core MUA TX empty interrupt"]
    EDGELOCK_APP_MUA_TX = 31,
    #[doc = "Edgelock Realtime Core MUA RX full interrupt"]
    EDGELOCK_RT_MUA_RX = 32,
    #[doc = "Edgelock Realtime Core MUA TX empty interrupt"]
    EDGELOCK_RT_MUA_TX = 33,
    #[doc = "Edgelock secure interrupt"]
    EDGELOCK_SECURE = 34,
    #[doc = "Edgelock non-secure interrupt"]
    EDGELOCK_NONSECURE = 35,
    #[doc = "Timer PWM module 1"]
    TPM1 = 36,
    #[doc = "Timer PWM module 2"]
    TPM2 = 37,
    #[doc = "Watchdog 1 Interrupt"]
    WDOG1 = 38,
    #[doc = "Watchdog 2 Interrupt"]
    WDOG2 = 39,
    #[doc = "AONMIX TRDC transfer error interrupt"]
    TRDC = 40,
    #[doc = "Serial Audio Interface 1"]
    SAI1 = 45,
    #[doc = "M33 PS Tag/Data Parity Error"]
    PS_PARITY_ERR = 46,
    #[doc = "M33 TCM ECC interrupt"]
    TCM_ECC = 47,
    #[doc = "M33 TCM Error interrupt"]
    TCM_ERR = 48,
    #[doc = "CAN2 interrupt"]
    CAN2 = 51,
    #[doc = "CAN2 error interrupt"]
    CAN2_ERROR = 52,
    #[doc = "Flexible IO 1 interrupt"]
    FLEXIO1 = 53,
    #[doc = "Flexible IO 2 interrupt"]
    FLEXIO2 = 54,
    #[doc = "FlexSPI controller interface interrupt 1"]
    FlexSPI1 = 55,
    #[doc = "General Purpose Input/Output 2 interrupt 0"]
    GPIO2_0 = 57,
    #[doc = "General Purpose Input/Output 2 interrupt 1"]
    GPIO2_1 = 58,
    #[doc = "General Purpose Input/Output 3 interrupt 0"]
    GPIO3_0 = 59,
    #[doc = "General Purpose Input/Output 3 interrupt 1"]
    GPIO3_1 = 60,
    #[doc = "Improved Inter-Integrated Circuit 2 interrupt"]
    I3C2 = 61,
    #[doc = "Low Power Inter-Integrated Circuit module 3"]
    LPI2C3 = 62,
    #[doc = "Low Power Inter-Integrated Circuit module 4"]
    LPI2C4 = 63,
    #[doc = "Low Power Periodic Interrupt Timer 2"]
    LPIT2 = 64,
    #[doc = "Low Power Serial Peripheral Interface 3"]
    LPSPI3 = 65,
    #[doc = "Low Power Serial Peripheral Interface 4"]
    LPSPI4 = 66,
    #[doc = "Low Power Timer 2"]
    LPTMR2 = 67,
    #[doc = "Low Power UART 3"]
    LPUART3 = 68,
    #[doc = "Low Power UART 4"]
    LPUART4 = 69,
    #[doc = "Low Power UART 5"]
    LPUART5 = 70,
    #[doc = "Low Power UART 6"]
    LPUART6 = 71,
    #[doc = "MTR Master error interrupt"]
    MTR_MASTER_ERR = 72,
    #[doc = "BBNSM Non-Secure interrupt"]
    BBNSM_NONSECURE = 73,
    #[doc = "System Counter compare interrupt"]
    SYS_CTR_COMPARE = 74,
    #[doc = "Timer PWM module 3"]
    TPM3 = 75,
    #[doc = "Timer PWM module 4"]
    TPM4 = 76,
    #[doc = "Timer PWM module 5"]
    TPM5 = 77,
    #[doc = "Timer PWM module 6"]
    TPM6 = 78,
    #[doc = "Watchdog 3 Interrupt"]
    WDOG3 = 79,
    #[doc = "Watchdog 4 Interrupt"]
    WDOG4 = 80,
    #[doc = "Watchdog 5 Interrupt"]
    WDOG5 = 81,
    #[doc = "WAKEUPMIX TRDC transfer error interrupt"]
    TRDC_WAKEUPMIX_ERR = 82,
    #[doc = "TempSensor interrupt"]
    TEMPMON = 83,
    #[doc = "ultra Secure Digital Host Controller interrupt 1"]
    uSDHC1 = 86,
    #[doc = "ultra Secure Digital Host Controller interrupt 2"]
    uSDHC2 = 87,
    #[doc = "MEGAMIX TRDC transfer error interrupt"]
    TRDC_MEGAMIX_ERR = 88,
    #[doc = "NIC_WRAPPER TRDC transfer error interrupt"]
    TRDC_NIC_WRAPPER_ERR = 89,
    #[doc = "DRAM controller Performance Monitor Interrupt"]
    DRAM_PERFMON = 90,
    #[doc = "DRAM controller Critical Interrupt"]
    DRAM_CRITICAL = 91,
    #[doc = "DRAM Phy Critical Interrupt"]
    DRAM_PHY_CRITICAL = 92,
    #[doc = "eDMA1 error interrupt"]
    DMA3_ERROR = 94,
    #[doc = "eDMA1 channel 0 interrupt"]
    DMA3_0 = 95,
    #[doc = "eDMA1 channel 1 interrupt"]
    DMA3_1 = 96,
    #[doc = "eDMA1 channel 2 interrupt"]
    DMA3_2 = 97,
    #[doc = "eDMA1 channel 3 interrupt"]
    DMA3_3 = 98,
    #[doc = "eDMA1 channel 4 interrupt"]
    DMA3_4 = 99,
    #[doc = "eDMA1 channel 5 interrupt"]
    DMA3_5 = 100,
    #[doc = "eDMA1 channel 6 interrupt"]
    DMA3_6 = 101,
    #[doc = "eDMA1 channel 7 interrupt"]
    DMA3_7 = 102,
    #[doc = "eDMA1 channel 8 interrupt"]
    DMA3_8 = 103,
    #[doc = "eDMA1 channel 9 interrupt"]
    DMA3_9 = 104,
    #[doc = "eDMA1 channel 10 interrupt"]
    DMA3_10 = 105,
    #[doc = "eDMA1 channel 11 interrupt"]
    DMA3_11 = 106,
    #[doc = "eDMA1 channel 12 interrupt"]
    DMA3_12 = 107,
    #[doc = "eDMA1 channel 13 interrupt"]
    DMA3_13 = 108,
    #[doc = "eDMA1 channel 14 interrupt"]
    DMA3_14 = 109,
    #[doc = "eDMA1 channel 15 interrupt"]
    DMA3_15 = 110,
    #[doc = "eDMA1 channel 16 interrupt"]
    DMA3_16 = 111,
    #[doc = "eDMA1 channel 17 interrupt"]
    DMA3_17 = 112,
    #[doc = "eDMA1 channel 18 interrupt"]
    DMA3_18 = 113,
    #[doc = "eDMA1 channel 19 interrupt"]
    DMA3_19 = 114,
    #[doc = "eDMA1 channel 20 interrupt"]
    DMA3_20 = 115,
    #[doc = "eDMA1 channel 21 interrupt"]
    DMA3_21 = 116,
    #[doc = "eDMA1 channel 22 interrupt"]
    DMA3_22 = 117,
    #[doc = "eDMA1 channel 23 interrupt"]
    DMA3_23 = 118,
    #[doc = "eDMA1 channel 24 interrupt"]
    DMA3_24 = 119,
    #[doc = "eDMA1 channel 25 interrupt"]
    DMA3_25 = 120,
    #[doc = "eDMA1 channel 26 interrupt"]
    DMA3_26 = 121,
    #[doc = "eDMA1 channel 27 interrupt"]
    DMA3_27 = 122,
    #[doc = "eDMA1 channel 28 interrupt"]
    DMA3_28 = 123,
    #[doc = "eDMA1 channel 29 interrupt"]
    DMA3_29 = 124,
    #[doc = "eDMA1 channel 30 interrupt"]
    DMA3_30 = 125,
    #[doc = "eDMA2 error interrupt"]
    DMA4_ERROR = 127,
    #[doc = "eDMA2 channel 0/1 interrupt"]
    DMA4_0_1 = 128,
    #[doc = "eDMA2 channel 2/3 interrupt"]
    DMA4_2_3 = 129,
    #[doc = "eDMA2 channel 4/5 interrupt"]
    DMA4_4_5 = 130,
    #[doc = "eDMA2 channel 6/7 interrupt"]
    DMA4_6_7 = 131,
    #[doc = "eDMA2 channel 8/9 interrupt"]
    DMA4_8_9 = 132,
    #[doc = "eDMA2 channel 10/11 interrupt"]
    DMA4_10_11 = 133,
    #[doc = "eDMA2 channel 12/13 interrupt"]
    DMA4_12_13 = 134,
    #[doc = "eDMA2 channel 14/15 interrupt"]
    DMA4_14_15 = 135,
    #[doc = "eDMA2 channel 16/17 interrupt"]
    DMA4_16_17 = 136,
    #[doc = "eDMA2 channel 18/19 interrupt"]
    DMA4_18_19 = 137,
    #[doc = "eDMA2 channel 20/21 interrupt"]
    DMA4_20_21 = 138,
    #[doc = "eDMA2 channel 22/23 interrupt"]
    DMA4_22_23 = 139,
    #[doc = "eDMA2 channel 24/25 interrupt"]
    DMA4_24_25 = 140,
    #[doc = "eDMA2 channel 26/27 interrupt"]
    DMA4_26_27 = 141,
    #[doc = "eDMA2 channel 28/29 interrupt"]
    DMA4_28_29 = 142,
    #[doc = "eDMA2 channel 30/31 interrupt"]
    DMA4_30_31 = 143,
    #[doc = "eDMA2 channel 32/33 interrupt"]
    DMA4_32_33 = 144,
    #[doc = "eDMA2 channel 34/35 interrupt"]
    DMA4_34_35 = 145,
    #[doc = "eDMA2 channel 36/37 interrupt"]
    DMA4_36_37 = 146,
    #[doc = "eDMA2 channel 38/39 interrupt"]
    DMA4_38_39 = 147,
    #[doc = "eDMA2 channel 40/41 interrupt"]
    DMA4_40_41 = 148,
    #[doc = "eDMA2 channel 42/43 interrupt"]
    DMA4_42_43 = 149,
    #[doc = "eDMA2 channel 44/45 interrupt"]
    DMA4_44_45 = 150,
    #[doc = "eDMA2 channel 46/47 interrupt"]
    DMA4_46_47 = 151,
    #[doc = "eDMA2 channel 48/49 interrupt"]
    DMA4_48_49 = 152,
    #[doc = "eDMA2 channel 50/51 interrupt"]
    DMA4_50_51 = 153,
    #[doc = "eDMA2 channel 52/53 interrupt"]
    DMA4_52_53 = 154,
    #[doc = "eDMA2 channel 54/55 interrupt"]
    DMA4_54_55 = 155,
    #[doc = "eDMA2 channel 56/57 interrupt"]
    DMA4_56_57 = 156,
    #[doc = "eDMA2 channel 58/59 interrupt"]
    DMA4_58_59 = 157,
    #[doc = "eDMA2 channel 60/61 interrupt"]
    DMA4_60_61 = 158,
    #[doc = "eDMA2 channel 62/63 interrupt"]
    DMA4_62_63 = 159,
    #[doc = "Debug Wakeup Interrupt"]
    DEBUG_WAKEUP = 160,
    #[doc = "Edgelock Group 1 reset source"]
    EDGELOCK_GROUP1_RST_SRC = 161,
    #[doc = "Edgelock Group 2 reset source"]
    EDGELOCK_GROUP2_RST_SRC_0 = 162,
    #[doc = "Edgelock Group 2 reset source"]
    EDGELOCK_GROUP2_RST_SRC_1 = 163,
    #[doc = "JTAGSW DAP MDM-AP SRC reset source"]
    DBG_TRACE_RST_SRC = 164,
    #[doc = "JTAGC SRC reset source"]
    JTAGC_RST_SRC = 165,
    #[doc = "CM33 SYSREQRST SRC reset source"]
    CM33_SYSREQRST_RST_SRC = 166,
    #[doc = "CM33 LOCKUP SRC reset source"]
    CM33_LOCKUP_RST_SRC = 167,
    #[doc = "Serial Audio Interface 2"]
    SAI2 = 170,
    #[doc = "Serial Audio Interface 3"]
    SAI3 = 171,
    #[doc = "ISI interrupt"]
    ISI = 172,
    #[doc = "PXP interrupt 0"]
    PXP_0 = 173,
    #[doc = "PXP interrupt 1"]
    PXP_1 = 174,
    #[doc = "CSI interrupt"]
    CSI = 175,
    #[doc = "LCDIF Sync Interrupt"]
    LCDIFv3 = 176,
    #[doc = "MIPI DSI Interrupt Request"]
    DSI = 177,
    #[doc = "Machine learning processor interrupt"]
    ML = 178,
    #[doc = "MAC 0 Receive / Trasmit Frame / Buffer Done"]
    ENET_MAC0_Rx_Tx_Done1 = 179,
    #[doc = "MAC 0 Receive / Trasmit Frame / Buffer Done"]
    ENET_MAC0_Rx_Tx_Done2 = 180,
    #[doc = "MAC 0 IRQ"]
    ENET = 181,
    #[doc = "MAC 0 1588 Timer Interrupt - synchronous"]
    ENET_1588 = 182,
    #[doc = "ENET QOS PMT interrupt"]
    ENET_QOS_PMT = 183,
    #[doc = "ENET QOS interrupt"]
    ENET_QOS = 184,
    #[doc = "USB-1 Wake-up Interrupt"]
    USB1_WAKEUP = 187,
    #[doc = "USB-2 Wake-up Interrupt"]
    USB2_WAKEUP = 188,
    #[doc = "General Purpose Input/Output 4 interrupt 0"]
    GPIO4_0 = 189,
    #[doc = "General Purpose Input/Output 4 interrupt 1"]
    GPIO4_1 = 190,
    #[doc = "Low Power Serial Peripheral Interface 5"]
    LPSPI5 = 191,
    #[doc = "Low Power Serial Peripheral Interface 6"]
    LPSPI6 = 192,
    #[doc = "Low Power Serial Peripheral Interface 7"]
    LPSPI7 = 193,
    #[doc = "Low Power Serial Peripheral Interface 8"]
    LPSPI8 = 194,
    #[doc = "Low Power Inter-Integrated Circuit module 5"]
    LPI2C5 = 195,
    #[doc = "Low Power Inter-Integrated Circuit module 6"]
    LPI2C6 = 196,
    #[doc = "Low Power Inter-Integrated Circuit module 7"]
    LPI2C7 = 197,
    #[doc = "Low Power Inter-Integrated Circuit module 8"]
    LPI2C8 = 198,
    #[doc = "PDM interrupt"]
    PDM_HWVAD_ERROR = 199,
    #[doc = "PDM interrupt"]
    PDM_HWVAD_EVENT = 200,
    #[doc = "PDM interrupt"]
    PDM_ERROR = 201,
    #[doc = "PDM interrupt"]
    PDM_EVENT = 202,
    #[doc = "AUDIO XCVR interrupt"]
    AUDIO_XCVR_0 = 203,
    #[doc = "AUDIO XCVR interrupt"]
    AUDIO_XCVR_1 = 204,
    #[doc = "ultra Secure Digital Host Controller interrupt 3"]
    uSDHC3 = 205,
    #[doc = "OCRAM MECC interrupt"]
    OCRAM_MECC_0 = 206,
    #[doc = "OCRAM MECC interrupt"]
    OCRAM_MECC_1 = 207,
    #[doc = "HSIOMIX TRDC transfer error interrupt"]
    TRDC_HSIOMIX_ERR = 208,
    #[doc = "MEDIAMIX TRDC transfer error interrupt"]
    TRDC_MEDIAMIX_ERR = 209,
    #[doc = "Low Power UART 7"]
    LPUART7 = 210,
    #[doc = "Low Power UART 8"]
    LPUART8 = 211,
    #[doc = "CM33 MCM interrupt"]
    CM33_MCM = 212,
    #[doc = "SFA interrupt"]
    SFA = 213,
    #[doc = "GIC600 INTERRUPT"]
    GIC600_0 = 214,
    #[doc = "GIC600 INTERRUPT"]
    GIC600_1 = 215,
    #[doc = "GIC600 INTERRUPT"]
    GIC600_2 = 216,
    #[doc = "ADC interrupt"]
    ADC_ER = 217,
    #[doc = "ADC interrupt"]
    ADC_WD = 218,
    #[doc = "ADC interrupt"]
    ADC_EOC = 219,
    #[doc = "I3C1 wakeup irq after double sync"]
    I3C1_WAKEUP = 221,
    #[doc = "I3C2 wakeup irq after double sync"]
    I3C2_WAKEUP = 222,
}

// SAFETY: each variant carries the external interrupt number defined by the
// chip's vendor headers, so `number` returns a valid NVIC line.
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}

// `#[interrupt]` handler support. The attribute macro (macro namespace)
// and the `Interrupt` alias (type namespace) share the name `interrupt`,
// so the macro's generated `interrupt::NAME;` existence check resolves.
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;

#[cfg(feature = "rt")]
#[doc(hidden)]
#[allow(dead_code)]
pub union Vector {
    handler: unsafe extern "C" fn(),
    reserved: usize,
}

#[cfg(feature = "rt")]
unsafe extern "C" {
    fn DAP();
    fn CTI_CM33();
    fn CTI_CA55();
    fn PMU();
    fn CACHE_ECC_ERR();
    fn CACHE_ECC_PARITY_ERR();
    fn CAN1();
    fn CAN1_ERROR();
    fn GPIO1_0();
    fn GPIO1_1();
    fn I3C1();
    fn LPI2C1();
    fn LPI2C2();
    fn LPIT1();
    fn LPSPI1();
    fn LPSPI2();
    fn LPTMR1();
    fn LPUART1();
    fn LPUART2();
    fn MU1_A();
    fn MU1_B();
    fn MU2_A();
    fn MU2_B();
    fn EDGELOCK_TRUST_MUA_RX();
    fn EDGELOCK_TRUST_MUA_TX();
    fn EDGELOCK_APP_MUA_RX();
    fn EDGELOCK_APP_MUA_TX();
    fn EDGELOCK_RT_MUA_RX();
    fn EDGELOCK_RT_MUA_TX();
    fn EDGELOCK_SECURE();
    fn EDGELOCK_NONSECURE();
    fn TPM1();
    fn TPM2();
    fn WDOG1();
    fn WDOG2();
    fn TRDC();
    fn SAI1();
    fn PS_PARITY_ERR();
    fn TCM_ECC();
    fn TCM_ERR();
    fn CAN2();
    fn CAN2_ERROR();
    fn FLEXIO1();
    fn FLEXIO2();
    fn FlexSPI1();
    fn GPIO2_0();
    fn GPIO2_1();
    fn GPIO3_0();
    fn GPIO3_1();
    fn I3C2();
    fn LPI2C3();
    fn LPI2C4();
    fn LPIT2();
    fn LPSPI3();
    fn LPSPI4();
    fn LPTMR2();
    fn LPUART3();
    fn LPUART4();
    fn LPUART5();
    fn LPUART6();
    fn MTR_MASTER_ERR();
    fn BBNSM_NONSECURE();
    fn SYS_CTR_COMPARE();
    fn TPM3();
    fn TPM4();
    fn TPM5();
    fn TPM6();
    fn WDOG3();
    fn WDOG4();
    fn WDOG5();
    fn TRDC_WAKEUPMIX_ERR();
    fn TEMPMON();
    fn uSDHC1();
    fn uSDHC2();
    fn TRDC_MEGAMIX_ERR();
    fn TRDC_NIC_WRAPPER_ERR();
    fn DRAM_PERFMON();
    fn DRAM_CRITICAL();
    fn DRAM_PHY_CRITICAL();
    fn DMA3_ERROR();
    fn DMA3_0();
    fn DMA3_1();
    fn DMA3_2();
    fn DMA3_3();
    fn DMA3_4();
    fn DMA3_5();
    fn DMA3_6();
    fn DMA3_7();
    fn DMA3_8();
    fn DMA3_9();
    fn DMA3_10();
    fn DMA3_11();
    fn DMA3_12();
    fn DMA3_13();
    fn DMA3_14();
    fn DMA3_15();
    fn DMA3_16();
    fn DMA3_17();
    fn DMA3_18();
    fn DMA3_19();
    fn DMA3_20();
    fn DMA3_21();
    fn DMA3_22();
    fn DMA3_23();
    fn DMA3_24();
    fn DMA3_25();
    fn DMA3_26();
    fn DMA3_27();
    fn DMA3_28();
    fn DMA3_29();
    fn DMA3_30();
    fn DMA4_ERROR();
    fn DMA4_0_1();
    fn DMA4_2_3();
    fn DMA4_4_5();
    fn DMA4_6_7();
    fn DMA4_8_9();
    fn DMA4_10_11();
    fn DMA4_12_13();
    fn DMA4_14_15();
    fn DMA4_16_17();
    fn DMA4_18_19();
    fn DMA4_20_21();
    fn DMA4_22_23();
    fn DMA4_24_25();
    fn DMA4_26_27();
    fn DMA4_28_29();
    fn DMA4_30_31();
    fn DMA4_32_33();
    fn DMA4_34_35();
    fn DMA4_36_37();
    fn DMA4_38_39();
    fn DMA4_40_41();
    fn DMA4_42_43();
    fn DMA4_44_45();
    fn DMA4_46_47();
    fn DMA4_48_49();
    fn DMA4_50_51();
    fn DMA4_52_53();
    fn DMA4_54_55();
    fn DMA4_56_57();
    fn DMA4_58_59();
    fn DMA4_60_61();
    fn DMA4_62_63();
    fn DEBUG_WAKEUP();
    fn EDGELOCK_GROUP1_RST_SRC();
    fn EDGELOCK_GROUP2_RST_SRC_0();
    fn EDGELOCK_GROUP2_RST_SRC_1();
    fn DBG_TRACE_RST_SRC();
    fn JTAGC_RST_SRC();
    fn CM33_SYSREQRST_RST_SRC();
    fn CM33_LOCKUP_RST_SRC();
    fn SAI2();
    fn SAI3();
    fn ISI();
    fn PXP_0();
    fn PXP_1();
    fn CSI();
    fn LCDIFv3();
    fn DSI();
    fn ML();
    fn ENET_MAC0_Rx_Tx_Done1();
    fn ENET_MAC0_Rx_Tx_Done2();
    fn ENET();
    fn ENET_1588();
    fn ENET_QOS_PMT();
    fn ENET_QOS();
    fn USB1_WAKEUP();
    fn USB2_WAKEUP();
    fn GPIO4_0();
    fn GPIO4_1();
    fn LPSPI5();
    fn LPSPI6();
    fn LPSPI7();
    fn LPSPI8();
    fn LPI2C5();
    fn LPI2C6();
    fn LPI2C7();
    fn LPI2C8();
    fn PDM_HWVAD_ERROR();
    fn PDM_HWVAD_EVENT();
    fn PDM_ERROR();
    fn PDM_EVENT();
    fn AUDIO_XCVR_0();
    fn AUDIO_XCVR_1();
    fn uSDHC3();
    fn OCRAM_MECC_0();
    fn OCRAM_MECC_1();
    fn TRDC_HSIOMIX_ERR();
    fn TRDC_MEDIAMIX_ERR();
    fn LPUART7();
    fn LPUART8();
    fn CM33_MCM();
    fn SFA();
    fn GIC600_0();
    fn GIC600_1();
    fn GIC600_2();
    fn ADC_ER();
    fn ADC_WD();
    fn ADC_EOC();
    fn I3C1_WAKEUP();
    fn I3C2_WAKEUP();
}

#[doc = "Device-specific interrupt portion of the vector table for imx93 (cm33)."]
#[cfg(feature = "rt")]
#[doc(hidden)]
#[unsafe(link_section = ".vector_table.interrupts")]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [Vector; 223] = [
    Vector { reserved: 0 },       // 0: reserved
    Vector { handler: DAP },      // 1: DAP
    Vector { reserved: 0 },       // 2: reserved
    Vector { handler: CTI_CM33 }, // 3: CTI_CM33
    Vector { handler: CTI_CA55 }, // 4: CTI_CA55
    Vector { handler: PMU },      // 5: PMU
    Vector {
        handler: CACHE_ECC_ERR,
    }, // 6: CACHE_ECC_ERR
    Vector {
        handler: CACHE_ECC_PARITY_ERR,
    }, // 7: CACHE_ECC_PARITY_ERR
    Vector { handler: CAN1 },     // 8: CAN1
    Vector {
        handler: CAN1_ERROR,
    }, // 9: CAN1_ERROR
    Vector { handler: GPIO1_0 },  // 10: GPIO1_0
    Vector { handler: GPIO1_1 },  // 11: GPIO1_1
    Vector { handler: I3C1 },     // 12: I3C1
    Vector { handler: LPI2C1 },   // 13: LPI2C1
    Vector { handler: LPI2C2 },   // 14: LPI2C2
    Vector { handler: LPIT1 },    // 15: LPIT1
    Vector { handler: LPSPI1 },   // 16: LPSPI1
    Vector { handler: LPSPI2 },   // 17: LPSPI2
    Vector { handler: LPTMR1 },   // 18: LPTMR1
    Vector { handler: LPUART1 },  // 19: LPUART1
    Vector { handler: LPUART2 },  // 20: LPUART2
    Vector { handler: MU1_A },    // 21: MU1_A
    Vector { handler: MU1_B },    // 22: MU1_B
    Vector { handler: MU2_A },    // 23: MU2_A
    Vector { handler: MU2_B },    // 24: MU2_B
    Vector { reserved: 0 },       // 25: reserved
    Vector { reserved: 0 },       // 26: reserved
    Vector { reserved: 0 },       // 27: reserved
    Vector {
        handler: EDGELOCK_TRUST_MUA_RX,
    }, // 28: EDGELOCK_TRUST_MUA_RX
    Vector {
        handler: EDGELOCK_TRUST_MUA_TX,
    }, // 29: EDGELOCK_TRUST_MUA_TX
    Vector {
        handler: EDGELOCK_APP_MUA_RX,
    }, // 30: EDGELOCK_APP_MUA_RX
    Vector {
        handler: EDGELOCK_APP_MUA_TX,
    }, // 31: EDGELOCK_APP_MUA_TX
    Vector {
        handler: EDGELOCK_RT_MUA_RX,
    }, // 32: EDGELOCK_RT_MUA_RX
    Vector {
        handler: EDGELOCK_RT_MUA_TX,
    }, // 33: EDGELOCK_RT_MUA_TX
    Vector {
        handler: EDGELOCK_SECURE,
    }, // 34: EDGELOCK_SECURE
    Vector {
        handler: EDGELOCK_NONSECURE,
    }, // 35: EDGELOCK_NONSECURE
    Vector { handler: TPM1 },     // 36: TPM1
    Vector { handler: TPM2 },     // 37: TPM2
    Vector { handler: WDOG1 },    // 38: WDOG1
    Vector { handler: WDOG2 },    // 39: WDOG2
    Vector { handler: TRDC },     // 40: TRDC
    Vector { reserved: 0 },       // 41: reserved
    Vector { reserved: 0 },       // 42: reserved
    Vector { reserved: 0 },       // 43: reserved
    Vector { reserved: 0 },       // 44: reserved
    Vector { handler: SAI1 },     // 45: SAI1
    Vector {
        handler: PS_PARITY_ERR,
    }, // 46: PS_PARITY_ERR
    Vector { handler: TCM_ECC },  // 47: TCM_ECC
    Vector { handler: TCM_ERR },  // 48: TCM_ERR
    Vector { reserved: 0 },       // 49: reserved
    Vector { reserved: 0 },       // 50: reserved
    Vector { handler: CAN2 },     // 51: CAN2
    Vector {
        handler: CAN2_ERROR,
    }, // 52: CAN2_ERROR
    Vector { handler: FLEXIO1 },  // 53: FLEXIO1
    Vector { handler: FLEXIO2 },  // 54: FLEXIO2
    Vector { handler: FlexSPI1 }, // 55: FlexSPI1
    Vector { reserved: 0 },       // 56: reserved
    Vector { handler: GPIO2_0 },  // 57: GPIO2_0
    Vector { handler: GPIO2_1 },  // 58: GPIO2_1
    Vector { handler: GPIO3_0 },  // 59: GPIO3_0
    Vector { handler: GPIO3_1 },  // 60: GPIO3_1
    Vector { handler: I3C2 },     // 61: I3C2
    Vector { handler: LPI2C3 },   // 62: LPI2C3
    Vector { handler: LPI2C4 },   // 63: LPI2C4
    Vector { handler: LPIT2 },    // 64: LPIT2
    Vector { handler: LPSPI3 },   // 65: LPSPI3
    Vector { handler: LPSPI4 },   // 66: LPSPI4
    Vector { handler: LPTMR2 },   // 67: LPTMR2
    Vector { handler: LPUART3 },  // 68: LPUART3
    Vector { handler: LPUART4 },  // 69: LPUART4
    Vector { handler: LPUART5 },  // 70: LPUART5
    Vector { handler: LPUART6 },  // 71: LPUART6
    Vector {
        handler: MTR_MASTER_ERR,
    }, // 72: MTR_MASTER_ERR
    Vector {
        handler: BBNSM_NONSECURE,
    }, // 73: BBNSM_NONSECURE
    Vector {
        handler: SYS_CTR_COMPARE,
    }, // 74: SYS_CTR_COMPARE
    Vector { handler: TPM3 },     // 75: TPM3
    Vector { handler: TPM4 },     // 76: TPM4
    Vector { handler: TPM5 },     // 77: TPM5
    Vector { handler: TPM6 },     // 78: TPM6
    Vector { handler: WDOG3 },    // 79: WDOG3
    Vector { handler: WDOG4 },    // 80: WDOG4
    Vector { handler: WDOG5 },    // 81: WDOG5
    Vector {
        handler: TRDC_WAKEUPMIX_ERR,
    }, // 82: TRDC_WAKEUPMIX_ERR
    Vector { handler: TEMPMON },  // 83: TEMPMON
    Vector { reserved: 0 },       // 84: reserved
    Vector { reserved: 0 },       // 85: reserved
    Vector { handler: uSDHC1 },   // 86: uSDHC1
    Vector { handler: uSDHC2 },   // 87: uSDHC2
    Vector {
        handler: TRDC_MEGAMIX_ERR,
    }, // 88: TRDC_MEGAMIX_ERR
    Vector {
        handler: TRDC_NIC_WRAPPER_ERR,
    }, // 89: TRDC_NIC_WRAPPER_ERR
    Vector {
        handler: DRAM_PERFMON,
    }, // 90: DRAM_PERFMON
    Vector {
        handler: DRAM_CRITICAL,
    }, // 91: DRAM_CRITICAL
    Vector {
        handler: DRAM_PHY_CRITICAL,
    }, // 92: DRAM_PHY_CRITICAL
    Vector { reserved: 0 },       // 93: reserved
    Vector {
        handler: DMA3_ERROR,
    }, // 94: DMA3_ERROR
    Vector { handler: DMA3_0 },   // 95: DMA3_0
    Vector { handler: DMA3_1 },   // 96: DMA3_1
    Vector { handler: DMA3_2 },   // 97: DMA3_2
    Vector { handler: DMA3_3 },   // 98: DMA3_3
    Vector { handler: DMA3_4 },   // 99: DMA3_4
    Vector { handler: DMA3_5 },   // 100: DMA3_5
    Vector { handler: DMA3_6 },   // 101: DMA3_6
    Vector { handler: DMA3_7 },   // 102: DMA3_7
    Vector { handler: DMA3_8 },   // 103: DMA3_8
    Vector { handler: DMA3_9 },   // 104: DMA3_9
    Vector { handler: DMA3_10 },  // 105: DMA3_10
    Vector { handler: DMA3_11 },  // 106: DMA3_11
    Vector { handler: DMA3_12 },  // 107: DMA3_12
    Vector { handler: DMA3_13 },  // 108: DMA3_13
    Vector { handler: DMA3_14 },  // 109: DMA3_14
    Vector { handler: DMA3_15 },  // 110: DMA3_15
    Vector { handler: DMA3_16 },  // 111: DMA3_16
    Vector { handler: DMA3_17 },  // 112: DMA3_17
    Vector { handler: DMA3_18 },  // 113: DMA3_18
    Vector { handler: DMA3_19 },  // 114: DMA3_19
    Vector { handler: DMA3_20 },  // 115: DMA3_20
    Vector { handler: DMA3_21 },  // 116: DMA3_21
    Vector { handler: DMA3_22 },  // 117: DMA3_22
    Vector { handler: DMA3_23 },  // 118: DMA3_23
    Vector { handler: DMA3_24 },  // 119: DMA3_24
    Vector { handler: DMA3_25 },  // 120: DMA3_25
    Vector { handler: DMA3_26 },  // 121: DMA3_26
    Vector { handler: DMA3_27 },  // 122: DMA3_27
    Vector { handler: DMA3_28 },  // 123: DMA3_28
    Vector { handler: DMA3_29 },  // 124: DMA3_29
    Vector { handler: DMA3_30 },  // 125: DMA3_30
    Vector { reserved: 0 },       // 126: reserved
    Vector {
        handler: DMA4_ERROR,
    }, // 127: DMA4_ERROR
    Vector { handler: DMA4_0_1 }, // 128: DMA4_0_1
    Vector { handler: DMA4_2_3 }, // 129: DMA4_2_3
    Vector { handler: DMA4_4_5 }, // 130: DMA4_4_5
    Vector { handler: DMA4_6_7 }, // 131: DMA4_6_7
    Vector { handler: DMA4_8_9 }, // 132: DMA4_8_9
    Vector {
        handler: DMA4_10_11,
    }, // 133: DMA4_10_11
    Vector {
        handler: DMA4_12_13,
    }, // 134: DMA4_12_13
    Vector {
        handler: DMA4_14_15,
    }, // 135: DMA4_14_15
    Vector {
        handler: DMA4_16_17,
    }, // 136: DMA4_16_17
    Vector {
        handler: DMA4_18_19,
    }, // 137: DMA4_18_19
    Vector {
        handler: DMA4_20_21,
    }, // 138: DMA4_20_21
    Vector {
        handler: DMA4_22_23,
    }, // 139: DMA4_22_23
    Vector {
        handler: DMA4_24_25,
    }, // 140: DMA4_24_25
    Vector {
        handler: DMA4_26_27,
    }, // 141: DMA4_26_27
    Vector {
        handler: DMA4_28_29,
    }, // 142: DMA4_28_29
    Vector {
        handler: DMA4_30_31,
    }, // 143: DMA4_30_31
    Vector {
        handler: DMA4_32_33,
    }, // 144: DMA4_32_33
    Vector {
        handler: DMA4_34_35,
    }, // 145: DMA4_34_35
    Vector {
        handler: DMA4_36_37,
    }, // 146: DMA4_36_37
    Vector {
        handler: DMA4_38_39,
    }, // 147: DMA4_38_39
    Vector {
        handler: DMA4_40_41,
    }, // 148: DMA4_40_41
    Vector {
        handler: DMA4_42_43,
    }, // 149: DMA4_42_43
    Vector {
        handler: DMA4_44_45,
    }, // 150: DMA4_44_45
    Vector {
        handler: DMA4_46_47,
    }, // 151: DMA4_46_47
    Vector {
        handler: DMA4_48_49,
    }, // 152: DMA4_48_49
    Vector {
        handler: DMA4_50_51,
    }, // 153: DMA4_50_51
    Vector {
        handler: DMA4_52_53,
    }, // 154: DMA4_52_53
    Vector {
        handler: DMA4_54_55,
    }, // 155: DMA4_54_55
    Vector {
        handler: DMA4_56_57,
    }, // 156: DMA4_56_57
    Vector {
        handler: DMA4_58_59,
    }, // 157: DMA4_58_59
    Vector {
        handler: DMA4_60_61,
    }, // 158: DMA4_60_61
    Vector {
        handler: DMA4_62_63,
    }, // 159: DMA4_62_63
    Vector {
        handler: DEBUG_WAKEUP,
    }, // 160: DEBUG_WAKEUP
    Vector {
        handler: EDGELOCK_GROUP1_RST_SRC,
    }, // 161: EDGELOCK_GROUP1_RST_SRC
    Vector {
        handler: EDGELOCK_GROUP2_RST_SRC_0,
    }, // 162: EDGELOCK_GROUP2_RST_SRC_0
    Vector {
        handler: EDGELOCK_GROUP2_RST_SRC_1,
    }, // 163: EDGELOCK_GROUP2_RST_SRC_1
    Vector {
        handler: DBG_TRACE_RST_SRC,
    }, // 164: DBG_TRACE_RST_SRC
    Vector {
        handler: JTAGC_RST_SRC,
    }, // 165: JTAGC_RST_SRC
    Vector {
        handler: CM33_SYSREQRST_RST_SRC,
    }, // 166: CM33_SYSREQRST_RST_SRC
    Vector {
        handler: CM33_LOCKUP_RST_SRC,
    }, // 167: CM33_LOCKUP_RST_SRC
    Vector { reserved: 0 },       // 168: reserved
    Vector { reserved: 0 },       // 169: reserved
    Vector { handler: SAI2 },     // 170: SAI2
    Vector { handler: SAI3 },     // 171: SAI3
    Vector { handler: ISI },      // 172: ISI
    Vector { handler: PXP_0 },    // 173: PXP_0
    Vector { handler: PXP_1 },    // 174: PXP_1
    Vector { handler: CSI },      // 175: CSI
    Vector { handler: LCDIFv3 },  // 176: LCDIFv3
    Vector { handler: DSI },      // 177: DSI
    Vector { handler: ML },       // 178: ML
    Vector {
        handler: ENET_MAC0_Rx_Tx_Done1,
    }, // 179: ENET_MAC0_Rx_Tx_Done1
    Vector {
        handler: ENET_MAC0_Rx_Tx_Done2,
    }, // 180: ENET_MAC0_Rx_Tx_Done2
    Vector { handler: ENET },     // 181: ENET
    Vector { handler: ENET_1588 }, // 182: ENET_1588
    Vector {
        handler: ENET_QOS_PMT,
    }, // 183: ENET_QOS_PMT
    Vector { handler: ENET_QOS }, // 184: ENET_QOS
    Vector { reserved: 0 },       // 185: reserved
    Vector { reserved: 0 },       // 186: reserved
    Vector {
        handler: USB1_WAKEUP,
    }, // 187: USB1_WAKEUP
    Vector {
        handler: USB2_WAKEUP,
    }, // 188: USB2_WAKEUP
    Vector { handler: GPIO4_0 },  // 189: GPIO4_0
    Vector { handler: GPIO4_1 },  // 190: GPIO4_1
    Vector { handler: LPSPI5 },   // 191: LPSPI5
    Vector { handler: LPSPI6 },   // 192: LPSPI6
    Vector { handler: LPSPI7 },   // 193: LPSPI7
    Vector { handler: LPSPI8 },   // 194: LPSPI8
    Vector { handler: LPI2C5 },   // 195: LPI2C5
    Vector { handler: LPI2C6 },   // 196: LPI2C6
    Vector { handler: LPI2C7 },   // 197: LPI2C7
    Vector { handler: LPI2C8 },   // 198: LPI2C8
    Vector {
        handler: PDM_HWVAD_ERROR,
    }, // 199: PDM_HWVAD_ERROR
    Vector {
        handler: PDM_HWVAD_EVENT,
    }, // 200: PDM_HWVAD_EVENT
    Vector { handler: PDM_ERROR }, // 201: PDM_ERROR
    Vector { handler: PDM_EVENT }, // 202: PDM_EVENT
    Vector {
        handler: AUDIO_XCVR_0,
    }, // 203: AUDIO_XCVR_0
    Vector {
        handler: AUDIO_XCVR_1,
    }, // 204: AUDIO_XCVR_1
    Vector { handler: uSDHC3 },   // 205: uSDHC3
    Vector {
        handler: OCRAM_MECC_0,
    }, // 206: OCRAM_MECC_0
    Vector {
        handler: OCRAM_MECC_1,
    }, // 207: OCRAM_MECC_1
    Vector {
        handler: TRDC_HSIOMIX_ERR,
    }, // 208: TRDC_HSIOMIX_ERR
    Vector {
        handler: TRDC_MEDIAMIX_ERR,
    }, // 209: TRDC_MEDIAMIX_ERR
    Vector { handler: LPUART7 },  // 210: LPUART7
    Vector { handler: LPUART8 },  // 211: LPUART8
    Vector { handler: CM33_MCM }, // 212: CM33_MCM
    Vector { handler: SFA },      // 213: SFA
    Vector { handler: GIC600_0 }, // 214: GIC600_0
    Vector { handler: GIC600_1 }, // 215: GIC600_1
    Vector { handler: GIC600_2 }, // 216: GIC600_2
    Vector { handler: ADC_ER },   // 217: ADC_ER
    Vector { handler: ADC_WD },   // 218: ADC_WD
    Vector { handler: ADC_EOC },  // 219: ADC_EOC
    Vector { reserved: 0 },       // 220: reserved
    Vector {
        handler: I3C1_WAKEUP,
    }, // 221: I3C1_WAKEUP
    Vector {
        handler: I3C2_WAKEUP,
    }, // 222: I3C2_WAKEUP
];