celox 0.10.1

Celox HDL Simulator
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

#[path = "test_utils/mod.rs"]
#[macro_use]
#[allow(unused_macros)]
mod test_utils;

all_backends! {
    fn concurrent_initial_shared_clock(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::shared_clock";
    }
    fn concurrent_initial_control_flow(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::control_flow";
    }
    fn concurrent_initial_clock_periods(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::clock_periods";
    }
    fn concurrent_initial_reset_only_clock(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::reset_only_clock";
    }
    fn concurrent_initial_simultaneous_edges(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::simultaneous_edges";
    }
    fn concurrent_initial_reset(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::reset";
    }
    fn concurrent_initial_reset_between_edges(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::reset_between_edges";
    }
    fn concurrent_initial_hierarchy(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::hierarchy";
    }
    fn concurrent_initial_mixed_edges(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::mixed_edges";
    }
    fn concurrent_initial_gated_drive(sim) {
        @omit_veryl;
        @ignore_on(sv);
        @case "concurrent_initial::gated_drive";
    }
}