#[doc = "Register `SVSMLCTL` reader"]
pub type R = crate::R<SvsmlctlSpec>;
#[doc = "Register `SVSMLCTL` writer"]
pub type W = crate::W<SvsmlctlSpec>;
#[doc = "SVS and SVM low side Reset Release Voltage Level Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Svsmlrrl {
#[doc = "0: SVS and SVM low side Reset Release Voltage Level 0"]
Svsmlrrl0 = 0,
#[doc = "1: SVS and SVM low side Reset Release Voltage Level 1"]
Svsmlrrl1 = 1,
#[doc = "2: SVS and SVM low side Reset Release Voltage Level 2"]
Svsmlrrl2 = 2,
#[doc = "3: SVS and SVM low side Reset Release Voltage Level 3"]
Svsmlrrl3 = 3,
#[doc = "4: SVS and SVM low side Reset Release Voltage Level 4"]
Svsmlrrl4 = 4,
#[doc = "5: SVS and SVM low side Reset Release Voltage Level 5"]
Svsmlrrl5 = 5,
#[doc = "6: SVS and SVM low side Reset Release Voltage Level 6"]
Svsmlrrl6 = 6,
#[doc = "7: SVS and SVM low side Reset Release Voltage Level 7"]
Svsmlrrl7 = 7,
}
impl From<Svsmlrrl> for u8 {
#[inline(always)]
fn from(variant: Svsmlrrl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Svsmlrrl {
type Ux = u8;
}
impl crate::IsEnum for Svsmlrrl {}
#[doc = "Field `SVSMLRRL` reader - SVS and SVM low side Reset Release Voltage Level Bit: 0"]
pub type SvsmlrrlR = crate::FieldReader<Svsmlrrl>;
impl SvsmlrrlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Svsmlrrl {
match self.bits {
0 => Svsmlrrl::Svsmlrrl0,
1 => Svsmlrrl::Svsmlrrl1,
2 => Svsmlrrl::Svsmlrrl2,
3 => Svsmlrrl::Svsmlrrl3,
4 => Svsmlrrl::Svsmlrrl4,
5 => Svsmlrrl::Svsmlrrl5,
6 => Svsmlrrl::Svsmlrrl6,
7 => Svsmlrrl::Svsmlrrl7,
_ => unreachable!(),
}
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn is_svsmlrrl_0(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl0
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn is_svsmlrrl_1(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl1
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn is_svsmlrrl_2(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl2
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn is_svsmlrrl_3(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl3
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 4"]
#[inline(always)]
pub fn is_svsmlrrl_4(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl4
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 5"]
#[inline(always)]
pub fn is_svsmlrrl_5(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl5
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 6"]
#[inline(always)]
pub fn is_svsmlrrl_6(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl6
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 7"]
#[inline(always)]
pub fn is_svsmlrrl_7(&self) -> bool {
*self == Svsmlrrl::Svsmlrrl7
}
}
#[doc = "Field `SVSMLRRL` writer - SVS and SVM low side Reset Release Voltage Level Bit: 0"]
pub type SvsmlrrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, Svsmlrrl, crate::Safe>;
impl<'a, REG> SvsmlrrlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SVS and SVM low side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn svsmlrrl_0(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl0)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn svsmlrrl_1(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl1)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn svsmlrrl_2(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl2)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn svsmlrrl_3(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl3)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 4"]
#[inline(always)]
pub fn svsmlrrl_4(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl4)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 5"]
#[inline(always)]
pub fn svsmlrrl_5(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl5)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 6"]
#[inline(always)]
pub fn svsmlrrl_6(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl6)
}
#[doc = "SVS and SVM low side Reset Release Voltage Level 7"]
#[inline(always)]
pub fn svsmlrrl_7(self) -> &'a mut crate::W<REG> {
self.variant(Svsmlrrl::Svsmlrrl7)
}
}
#[doc = "Field `SVSMLDLYST` reader - SVS and SVM low side delay status"]
pub type SvsmldlystR = crate::BitReader;
#[doc = "Field `SVSMLDLYST` writer - SVS and SVM low side delay status"]
pub type SvsmldlystW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSLMD` reader - SVS low side mode"]
pub type SvslmdR = crate::BitReader;
#[doc = "Field `SVSLMD` writer - SVS low side mode"]
pub type SvslmdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSMLEVM` reader - SVS and SVM low side event mask"]
pub type SvsmlevmR = crate::BitReader;
#[doc = "Field `SVSMLEVM` writer - SVS and SVM low side event mask"]
pub type SvsmlevmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSMLACE` reader - SVS and SVM low side auto control enable"]
pub type SvsmlaceR = crate::BitReader;
#[doc = "Field `SVSMLACE` writer - SVS and SVM low side auto control enable"]
pub type SvsmlaceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "SVS low side reset voltage level Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Svslrvl {
#[doc = "0: SVS low side Reset Release Voltage Level 0"]
Svslrvl0 = 0,
#[doc = "1: SVS low side Reset Release Voltage Level 1"]
Svslrvl1 = 1,
#[doc = "2: SVS low side Reset Release Voltage Level 2"]
Svslrvl2 = 2,
#[doc = "3: SVS low side Reset Release Voltage Level 3"]
Svslrvl3 = 3,
}
impl From<Svslrvl> for u8 {
#[inline(always)]
fn from(variant: Svslrvl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Svslrvl {
type Ux = u8;
}
impl crate::IsEnum for Svslrvl {}
#[doc = "Field `SVSLRVL` reader - SVS low side reset voltage level Bit: 0"]
pub type SvslrvlR = crate::FieldReader<Svslrvl>;
impl SvslrvlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Svslrvl {
match self.bits {
0 => Svslrvl::Svslrvl0,
1 => Svslrvl::Svslrvl1,
2 => Svslrvl::Svslrvl2,
3 => Svslrvl::Svslrvl3,
_ => unreachable!(),
}
}
#[doc = "SVS low side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn is_svslrvl_0(&self) -> bool {
*self == Svslrvl::Svslrvl0
}
#[doc = "SVS low side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn is_svslrvl_1(&self) -> bool {
*self == Svslrvl::Svslrvl1
}
#[doc = "SVS low side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn is_svslrvl_2(&self) -> bool {
*self == Svslrvl::Svslrvl2
}
#[doc = "SVS low side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn is_svslrvl_3(&self) -> bool {
*self == Svslrvl::Svslrvl3
}
}
#[doc = "Field `SVSLRVL` writer - SVS low side reset voltage level Bit: 0"]
pub type SvslrvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Svslrvl, crate::Safe>;
impl<'a, REG> SvslrvlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SVS low side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn svslrvl_0(self) -> &'a mut crate::W<REG> {
self.variant(Svslrvl::Svslrvl0)
}
#[doc = "SVS low side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn svslrvl_1(self) -> &'a mut crate::W<REG> {
self.variant(Svslrvl::Svslrvl1)
}
#[doc = "SVS low side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn svslrvl_2(self) -> &'a mut crate::W<REG> {
self.variant(Svslrvl::Svslrvl2)
}
#[doc = "SVS low side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn svslrvl_3(self) -> &'a mut crate::W<REG> {
self.variant(Svslrvl::Svslrvl3)
}
}
#[doc = "Field `SVSLE` reader - SVS low side enable"]
pub type SvsleR = crate::BitReader;
#[doc = "Field `SVSLE` writer - SVS low side enable"]
pub type SvsleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSLFP` reader - SVS low side full performace mode"]
pub type SvslfpR = crate::BitReader;
#[doc = "Field `SVSLFP` writer - SVS low side full performace mode"]
pub type SvslfpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMLOVPE` reader - SVM low side over-voltage enable"]
pub type SvmlovpeR = crate::BitReader;
#[doc = "Field `SVMLOVPE` writer - SVM low side over-voltage enable"]
pub type SvmlovpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMLE` reader - SVM low side enable"]
pub type SvmleR = crate::BitReader;
#[doc = "Field `SVMLE` writer - SVM low side enable"]
pub type SvmleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMLFP` reader - SVM low side full performace mode"]
pub type SvmlfpR = crate::BitReader;
#[doc = "Field `SVMLFP` writer - SVM low side full performace mode"]
pub type SvmlfpW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - SVS and SVM low side Reset Release Voltage Level Bit: 0"]
#[inline(always)]
pub fn svsmlrrl(&self) -> SvsmlrrlR {
SvsmlrrlR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - SVS and SVM low side delay status"]
#[inline(always)]
pub fn svsmldlyst(&self) -> SvsmldlystR {
SvsmldlystR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - SVS low side mode"]
#[inline(always)]
pub fn svslmd(&self) -> SvslmdR {
SvslmdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - SVS and SVM low side event mask"]
#[inline(always)]
pub fn svsmlevm(&self) -> SvsmlevmR {
SvsmlevmR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - SVS and SVM low side auto control enable"]
#[inline(always)]
pub fn svsmlace(&self) -> SvsmlaceR {
SvsmlaceR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - SVS low side reset voltage level Bit: 0"]
#[inline(always)]
pub fn svslrvl(&self) -> SvslrvlR {
SvslrvlR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - SVS low side enable"]
#[inline(always)]
pub fn svsle(&self) -> SvsleR {
SvsleR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - SVS low side full performace mode"]
#[inline(always)]
pub fn svslfp(&self) -> SvslfpR {
SvslfpR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - SVM low side over-voltage enable"]
#[inline(always)]
pub fn svmlovpe(&self) -> SvmlovpeR {
SvmlovpeR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - SVM low side enable"]
#[inline(always)]
pub fn svmle(&self) -> SvmleR {
SvmleR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - SVM low side full performace mode"]
#[inline(always)]
pub fn svmlfp(&self) -> SvmlfpR {
SvmlfpR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - SVS and SVM low side Reset Release Voltage Level Bit: 0"]
#[inline(always)]
pub fn svsmlrrl(&mut self) -> SvsmlrrlW<'_, SvsmlctlSpec> {
SvsmlrrlW::new(self, 0)
}
#[doc = "Bit 3 - SVS and SVM low side delay status"]
#[inline(always)]
pub fn svsmldlyst(&mut self) -> SvsmldlystW<'_, SvsmlctlSpec> {
SvsmldlystW::new(self, 3)
}
#[doc = "Bit 4 - SVS low side mode"]
#[inline(always)]
pub fn svslmd(&mut self) -> SvslmdW<'_, SvsmlctlSpec> {
SvslmdW::new(self, 4)
}
#[doc = "Bit 6 - SVS and SVM low side event mask"]
#[inline(always)]
pub fn svsmlevm(&mut self) -> SvsmlevmW<'_, SvsmlctlSpec> {
SvsmlevmW::new(self, 6)
}
#[doc = "Bit 7 - SVS and SVM low side auto control enable"]
#[inline(always)]
pub fn svsmlace(&mut self) -> SvsmlaceW<'_, SvsmlctlSpec> {
SvsmlaceW::new(self, 7)
}
#[doc = "Bits 8:9 - SVS low side reset voltage level Bit: 0"]
#[inline(always)]
pub fn svslrvl(&mut self) -> SvslrvlW<'_, SvsmlctlSpec> {
SvslrvlW::new(self, 8)
}
#[doc = "Bit 10 - SVS low side enable"]
#[inline(always)]
pub fn svsle(&mut self) -> SvsleW<'_, SvsmlctlSpec> {
SvsleW::new(self, 10)
}
#[doc = "Bit 11 - SVS low side full performace mode"]
#[inline(always)]
pub fn svslfp(&mut self) -> SvslfpW<'_, SvsmlctlSpec> {
SvslfpW::new(self, 11)
}
#[doc = "Bit 12 - SVM low side over-voltage enable"]
#[inline(always)]
pub fn svmlovpe(&mut self) -> SvmlovpeW<'_, SvsmlctlSpec> {
SvmlovpeW::new(self, 12)
}
#[doc = "Bit 14 - SVM low side enable"]
#[inline(always)]
pub fn svmle(&mut self) -> SvmleW<'_, SvsmlctlSpec> {
SvmleW::new(self, 14)
}
#[doc = "Bit 15 - SVM low side full performace mode"]
#[inline(always)]
pub fn svmlfp(&mut self) -> SvmlfpW<'_, SvsmlctlSpec> {
SvmlfpW::new(self, 15)
}
}
#[doc = "SVS and SVM low side control register\n\nYou can [`read`](crate::Reg::read) this register and get [`svsmlctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svsmlctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SvsmlctlSpec;
impl crate::RegisterSpec for SvsmlctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`svsmlctl::R`](R) reader structure"]
impl crate::Readable for SvsmlctlSpec {}
#[doc = "`write(|w| ..)` method takes [`svsmlctl::W`](W) writer structure"]
impl crate::Writable for SvsmlctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SVSMLCTL to value 0"]
impl crate::Resettable for SvsmlctlSpec {}