#[doc = "Register `SVSMHCTL` reader"]
pub type R = crate::R<SvsmhctlSpec>;
#[doc = "Register `SVSMHCTL` writer"]
pub type W = crate::W<SvsmhctlSpec>;
#[doc = "SVS and SVM high side Reset Release Voltage Level Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Svsmhrrl {
#[doc = "0: SVS and SVM high side Reset Release Voltage Level 0"]
Svsmhrrl0 = 0,
#[doc = "1: SVS and SVM high side Reset Release Voltage Level 1"]
Svsmhrrl1 = 1,
#[doc = "2: SVS and SVM high side Reset Release Voltage Level 2"]
Svsmhrrl2 = 2,
#[doc = "3: SVS and SVM high side Reset Release Voltage Level 3"]
Svsmhrrl3 = 3,
#[doc = "4: SVS and SVM high side Reset Release Voltage Level 4"]
Svsmhrrl4 = 4,
#[doc = "5: SVS and SVM high side Reset Release Voltage Level 5"]
Svsmhrrl5 = 5,
#[doc = "6: SVS and SVM high side Reset Release Voltage Level 6"]
Svsmhrrl6 = 6,
#[doc = "7: SVS and SVM high side Reset Release Voltage Level 7"]
Svsmhrrl7 = 7,
}
impl From<Svsmhrrl> for u8 {
#[inline(always)]
fn from(variant: Svsmhrrl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Svsmhrrl {
type Ux = u8;
}
impl crate::IsEnum for Svsmhrrl {}
#[doc = "Field `SVSMHRRL` reader - SVS and SVM high side Reset Release Voltage Level Bit: 0"]
pub type SvsmhrrlR = crate::FieldReader<Svsmhrrl>;
impl SvsmhrrlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Svsmhrrl {
match self.bits {
0 => Svsmhrrl::Svsmhrrl0,
1 => Svsmhrrl::Svsmhrrl1,
2 => Svsmhrrl::Svsmhrrl2,
3 => Svsmhrrl::Svsmhrrl3,
4 => Svsmhrrl::Svsmhrrl4,
5 => Svsmhrrl::Svsmhrrl5,
6 => Svsmhrrl::Svsmhrrl6,
7 => Svsmhrrl::Svsmhrrl7,
_ => unreachable!(),
}
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn is_svsmhrrl_0(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl0
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn is_svsmhrrl_1(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl1
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn is_svsmhrrl_2(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl2
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn is_svsmhrrl_3(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl3
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 4"]
#[inline(always)]
pub fn is_svsmhrrl_4(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl4
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 5"]
#[inline(always)]
pub fn is_svsmhrrl_5(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl5
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 6"]
#[inline(always)]
pub fn is_svsmhrrl_6(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl6
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 7"]
#[inline(always)]
pub fn is_svsmhrrl_7(&self) -> bool {
*self == Svsmhrrl::Svsmhrrl7
}
}
#[doc = "Field `SVSMHRRL` writer - SVS and SVM high side Reset Release Voltage Level Bit: 0"]
pub type SvsmhrrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, Svsmhrrl, crate::Safe>;
impl<'a, REG> SvsmhrrlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SVS and SVM high side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn svsmhrrl_0(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl0)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn svsmhrrl_1(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl1)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn svsmhrrl_2(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl2)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn svsmhrrl_3(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl3)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 4"]
#[inline(always)]
pub fn svsmhrrl_4(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl4)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 5"]
#[inline(always)]
pub fn svsmhrrl_5(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl5)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 6"]
#[inline(always)]
pub fn svsmhrrl_6(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl6)
}
#[doc = "SVS and SVM high side Reset Release Voltage Level 7"]
#[inline(always)]
pub fn svsmhrrl_7(self) -> &'a mut crate::W<REG> {
self.variant(Svsmhrrl::Svsmhrrl7)
}
}
#[doc = "Field `SVSMHDLYST` reader - SVS and SVM high side delay status"]
pub type SvsmhdlystR = crate::BitReader;
#[doc = "Field `SVSMHDLYST` writer - SVS and SVM high side delay status"]
pub type SvsmhdlystW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSHMD` reader - SVS high side mode"]
pub type SvshmdR = crate::BitReader;
#[doc = "Field `SVSHMD` writer - SVS high side mode"]
pub type SvshmdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSMHEVM` reader - SVS and SVM high side event mask"]
pub type SvsmhevmR = crate::BitReader;
#[doc = "Field `SVSMHEVM` writer - SVS and SVM high side event mask"]
pub type SvsmhevmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSMHACE` reader - SVS and SVM high side auto control enable"]
pub type SvsmhaceR = crate::BitReader;
#[doc = "Field `SVSMHACE` writer - SVS and SVM high side auto control enable"]
pub type SvsmhaceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "SVS high side reset voltage level Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Svshrvl {
#[doc = "0: SVS high side Reset Release Voltage Level 0"]
Svshrvl0 = 0,
#[doc = "1: SVS high side Reset Release Voltage Level 1"]
Svshrvl1 = 1,
#[doc = "2: SVS high side Reset Release Voltage Level 2"]
Svshrvl2 = 2,
#[doc = "3: SVS high side Reset Release Voltage Level 3"]
Svshrvl3 = 3,
}
impl From<Svshrvl> for u8 {
#[inline(always)]
fn from(variant: Svshrvl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Svshrvl {
type Ux = u8;
}
impl crate::IsEnum for Svshrvl {}
#[doc = "Field `SVSHRVL` reader - SVS high side reset voltage level Bit: 0"]
pub type SvshrvlR = crate::FieldReader<Svshrvl>;
impl SvshrvlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Svshrvl {
match self.bits {
0 => Svshrvl::Svshrvl0,
1 => Svshrvl::Svshrvl1,
2 => Svshrvl::Svshrvl2,
3 => Svshrvl::Svshrvl3,
_ => unreachable!(),
}
}
#[doc = "SVS high side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn is_svshrvl_0(&self) -> bool {
*self == Svshrvl::Svshrvl0
}
#[doc = "SVS high side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn is_svshrvl_1(&self) -> bool {
*self == Svshrvl::Svshrvl1
}
#[doc = "SVS high side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn is_svshrvl_2(&self) -> bool {
*self == Svshrvl::Svshrvl2
}
#[doc = "SVS high side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn is_svshrvl_3(&self) -> bool {
*self == Svshrvl::Svshrvl3
}
}
#[doc = "Field `SVSHRVL` writer - SVS high side reset voltage level Bit: 0"]
pub type SvshrvlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Svshrvl, crate::Safe>;
impl<'a, REG> SvshrvlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SVS high side Reset Release Voltage Level 0"]
#[inline(always)]
pub fn svshrvl_0(self) -> &'a mut crate::W<REG> {
self.variant(Svshrvl::Svshrvl0)
}
#[doc = "SVS high side Reset Release Voltage Level 1"]
#[inline(always)]
pub fn svshrvl_1(self) -> &'a mut crate::W<REG> {
self.variant(Svshrvl::Svshrvl1)
}
#[doc = "SVS high side Reset Release Voltage Level 2"]
#[inline(always)]
pub fn svshrvl_2(self) -> &'a mut crate::W<REG> {
self.variant(Svshrvl::Svshrvl2)
}
#[doc = "SVS high side Reset Release Voltage Level 3"]
#[inline(always)]
pub fn svshrvl_3(self) -> &'a mut crate::W<REG> {
self.variant(Svshrvl::Svshrvl3)
}
}
#[doc = "Field `SVSHE` reader - SVS high side enable"]
pub type SvsheR = crate::BitReader;
#[doc = "Field `SVSHE` writer - SVS high side enable"]
pub type SvsheW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSHFP` reader - SVS high side full performace mode"]
pub type SvshfpR = crate::BitReader;
#[doc = "Field `SVSHFP` writer - SVS high side full performace mode"]
pub type SvshfpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMHOVPE` reader - SVM high side over-voltage enable"]
pub type SvmhovpeR = crate::BitReader;
#[doc = "Field `SVMHOVPE` writer - SVM high side over-voltage enable"]
pub type SvmhovpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMHE` reader - SVM high side enable"]
pub type SvmheR = crate::BitReader;
#[doc = "Field `SVMHE` writer - SVM high side enable"]
pub type SvmheW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVMHFP` reader - SVM high side full performace mode"]
pub type SvmhfpR = crate::BitReader;
#[doc = "Field `SVMHFP` writer - SVM high side full performace mode"]
pub type SvmhfpW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - SVS and SVM high side Reset Release Voltage Level Bit: 0"]
#[inline(always)]
pub fn svsmhrrl(&self) -> SvsmhrrlR {
SvsmhrrlR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - SVS and SVM high side delay status"]
#[inline(always)]
pub fn svsmhdlyst(&self) -> SvsmhdlystR {
SvsmhdlystR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - SVS high side mode"]
#[inline(always)]
pub fn svshmd(&self) -> SvshmdR {
SvshmdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - SVS and SVM high side event mask"]
#[inline(always)]
pub fn svsmhevm(&self) -> SvsmhevmR {
SvsmhevmR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - SVS and SVM high side auto control enable"]
#[inline(always)]
pub fn svsmhace(&self) -> SvsmhaceR {
SvsmhaceR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - SVS high side reset voltage level Bit: 0"]
#[inline(always)]
pub fn svshrvl(&self) -> SvshrvlR {
SvshrvlR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - SVS high side enable"]
#[inline(always)]
pub fn svshe(&self) -> SvsheR {
SvsheR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - SVS high side full performace mode"]
#[inline(always)]
pub fn svshfp(&self) -> SvshfpR {
SvshfpR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - SVM high side over-voltage enable"]
#[inline(always)]
pub fn svmhovpe(&self) -> SvmhovpeR {
SvmhovpeR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - SVM high side enable"]
#[inline(always)]
pub fn svmhe(&self) -> SvmheR {
SvmheR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - SVM high side full performace mode"]
#[inline(always)]
pub fn svmhfp(&self) -> SvmhfpR {
SvmhfpR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - SVS and SVM high side Reset Release Voltage Level Bit: 0"]
#[inline(always)]
pub fn svsmhrrl(&mut self) -> SvsmhrrlW<'_, SvsmhctlSpec> {
SvsmhrrlW::new(self, 0)
}
#[doc = "Bit 3 - SVS and SVM high side delay status"]
#[inline(always)]
pub fn svsmhdlyst(&mut self) -> SvsmhdlystW<'_, SvsmhctlSpec> {
SvsmhdlystW::new(self, 3)
}
#[doc = "Bit 4 - SVS high side mode"]
#[inline(always)]
pub fn svshmd(&mut self) -> SvshmdW<'_, SvsmhctlSpec> {
SvshmdW::new(self, 4)
}
#[doc = "Bit 6 - SVS and SVM high side event mask"]
#[inline(always)]
pub fn svsmhevm(&mut self) -> SvsmhevmW<'_, SvsmhctlSpec> {
SvsmhevmW::new(self, 6)
}
#[doc = "Bit 7 - SVS and SVM high side auto control enable"]
#[inline(always)]
pub fn svsmhace(&mut self) -> SvsmhaceW<'_, SvsmhctlSpec> {
SvsmhaceW::new(self, 7)
}
#[doc = "Bits 8:9 - SVS high side reset voltage level Bit: 0"]
#[inline(always)]
pub fn svshrvl(&mut self) -> SvshrvlW<'_, SvsmhctlSpec> {
SvshrvlW::new(self, 8)
}
#[doc = "Bit 10 - SVS high side enable"]
#[inline(always)]
pub fn svshe(&mut self) -> SvsheW<'_, SvsmhctlSpec> {
SvsheW::new(self, 10)
}
#[doc = "Bit 11 - SVS high side full performace mode"]
#[inline(always)]
pub fn svshfp(&mut self) -> SvshfpW<'_, SvsmhctlSpec> {
SvshfpW::new(self, 11)
}
#[doc = "Bit 12 - SVM high side over-voltage enable"]
#[inline(always)]
pub fn svmhovpe(&mut self) -> SvmhovpeW<'_, SvsmhctlSpec> {
SvmhovpeW::new(self, 12)
}
#[doc = "Bit 14 - SVM high side enable"]
#[inline(always)]
pub fn svmhe(&mut self) -> SvmheW<'_, SvsmhctlSpec> {
SvmheW::new(self, 14)
}
#[doc = "Bit 15 - SVM high side full performace mode"]
#[inline(always)]
pub fn svmhfp(&mut self) -> SvmhfpW<'_, SvsmhctlSpec> {
SvmhfpW::new(self, 15)
}
}
#[doc = "SVS and SVM high side control register\n\nYou can [`read`](crate::Reg::read) this register and get [`svsmhctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`svsmhctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SvsmhctlSpec;
impl crate::RegisterSpec for SvsmhctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`svsmhctl::R`](R) reader structure"]
impl crate::Readable for SvsmhctlSpec {}
#[doc = "`write(|w| ..)` method takes [`svsmhctl::W`](W) writer structure"]
impl crate::Writable for SvsmhctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SVSMHCTL to value 0"]
impl crate::Resettable for SvsmhctlSpec {}