#![feature(abi_msp430_interrupt)]
#![feature(const_fn_trait_bound)]
#![doc = "Peripheral access API for CC430F5137 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[allow(unused_imports)]
use generic::*;
#[doc = "Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
#[cfg(feature = "rt")]
pub use msp430_rt::interrupt;
#[cfg(feature = "rt")]
unsafe extern "msp430-interrupt" {
fn AES();
fn RTC();
fn PORT2();
fn PORT1();
fn TIMER1_A1();
fn TIMER1_A0();
fn DMA();
fn CC1101();
fn TIMER0_A1();
fn TIMER0_A0();
fn ADC12();
fn USCI_B0();
fn USCI_A0();
fn WDT();
fn COMP_B();
fn UNMI();
fn SYSNMI();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "msp430-interrupt" fn(),
_reserved: u16,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[unsafe(link_section = ".vector_table.interrupts")]
#[unsafe(no_mangle)]
#[used]
pub static __INTERRUPTS: [Vector; 63] = [
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: AES },
Vector { _handler: RTC },
Vector { _reserved: 0 },
Vector { _handler: PORT2 },
Vector { _handler: PORT1 },
Vector {
_handler: TIMER1_A1,
},
Vector {
_handler: TIMER1_A0,
},
Vector { _handler: DMA },
Vector { _handler: CC1101 },
Vector {
_handler: TIMER0_A1,
},
Vector {
_handler: TIMER0_A0,
},
Vector { _handler: ADC12 },
Vector { _handler: USCI_B0 },
Vector { _handler: USCI_A0 },
Vector { _handler: WDT },
Vector { _handler: COMP_B },
Vector { _handler: UNMI },
Vector { _handler: SYSNMI },
];
#[doc = r"Enumeration of all the interrupts. This enum is seldom used in application or library crates. It is present primarily for documenting the device's implemented interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "45 - 0xFFDA AES"]
AES = 45,
#[doc = "46 - 0xFFDC RTC"]
RTC = 46,
#[doc = "48 - 0xFFE0 Port 2"]
PORT2 = 48,
#[doc = "49 - 0xFFE2 Port 1"]
PORT1 = 49,
#[doc = "50 - 0xFFE4 Timer1_A3 CC1-2, TA1"]
TIMER1_A1 = 50,
#[doc = "51 - 0xFFE6 Timer1_A3 CC0"]
TIMER1_A0 = 51,
#[doc = "52 - 0xFFE8 DMA"]
DMA = 52,
#[doc = "53 - 0xFFEA CC1101 Radio Interface"]
CC1101 = 53,
#[doc = "54 - 0xFFEC Timer0_A5 CC1-4, TA"]
TIMER0_A1 = 54,
#[doc = "55 - 0xFFEE Timer0_A5 CC0"]
TIMER0_A0 = 55,
#[doc = "56 - 0xFFF0 ADC"]
ADC12 = 56,
#[doc = "57 - 0xFFF2 USCI B0 Receive/Transmit"]
USCI_B0 = 57,
#[doc = "58 - 0xFFF4 USCI A0 Receive/Transmit"]
USCI_A0 = 58,
#[doc = "59 - 0xFFF6 Watchdog Timer"]
WDT = 59,
#[doc = "60 - 0xFFF8 Comparator B"]
COMP_B = 60,
#[doc = "61 - 0xFFFA User Non-maskable"]
UNMI = 61,
#[doc = "62 - 0xFFFC System Non-maskable"]
SYSNMI = 62,
}
#[doc = "Port Mapping Port 1"]
pub type PortMappingPort1 = crate::Periph<port_mapping_port_1::RegisterBlock, 0x01c8>;
impl core::fmt::Debug for PortMappingPort1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortMappingPort1").finish()
}
}
#[doc = "Port Mapping Port 1"]
pub mod port_mapping_port_1;
#[doc = "Port Mapping Port 2"]
pub type PortMappingPort2 = crate::Periph<port_mapping_port_2::RegisterBlock, 0x01d0>;
impl core::fmt::Debug for PortMappingPort2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortMappingPort2").finish()
}
}
#[doc = "Port Mapping Port 2"]
pub mod port_mapping_port_2;
#[doc = "Port Mapping Port 3"]
pub type PortMappingPort3 = crate::Periph<port_mapping_port_3::RegisterBlock, 0x01d8>;
impl core::fmt::Debug for PortMappingPort3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortMappingPort3").finish()
}
}
#[doc = "Port Mapping Port 3"]
pub mod port_mapping_port_3;
#[doc = "Port 1/2"]
pub type Port1_2 = crate::Periph<port_1_2::RegisterBlock, 0x0200>;
impl core::fmt::Debug for Port1_2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Port1_2").finish()
}
}
#[doc = "Port 1/2"]
pub mod port_1_2;
#[doc = "Port 3"]
pub type Port3 = crate::Periph<port_3::RegisterBlock, 0x0220>;
impl core::fmt::Debug for Port3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Port3").finish()
}
}
#[doc = "Port 3"]
pub mod port_3;
#[doc = "Port 5"]
pub type Port5 = crate::Periph<port_5::RegisterBlock, 0x0240>;
impl core::fmt::Debug for Port5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Port5").finish()
}
}
#[doc = "Port 5"]
pub mod port_5;
#[doc = "RTC Real Time Clock"]
pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x04a0>;
impl core::fmt::Debug for Rtc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rtc").finish()
}
}
#[doc = "RTC Real Time Clock"]
pub mod rtc;
#[doc = "USCI_A0 UART Mode"]
pub type UsciA0UartMode = crate::Periph<usci_a0_uart_mode::RegisterBlock, 0x05c0>;
impl core::fmt::Debug for UsciA0UartMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA0UartMode").finish()
}
}
#[doc = "USCI_A0 UART Mode"]
pub mod usci_a0_uart_mode;
#[doc = "USCI_A0 SPI Mode"]
pub type UsciA0SpiMode = crate::Periph<usci_a0_spi_mode::RegisterBlock, 0x05c0>;
impl core::fmt::Debug for UsciA0SpiMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA0SpiMode").finish()
}
}
#[doc = "USCI_A0 SPI Mode"]
pub mod usci_a0_spi_mode;
#[doc = "USCI_B0 I2C Mode"]
pub type UsciB0I2cMode = crate::Periph<usci_b0_i2c_mode::RegisterBlock, 0x05e0>;
impl core::fmt::Debug for UsciB0I2cMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciB0I2cMode").finish()
}
}
#[doc = "USCI_B0 I2C Mode"]
pub mod usci_b0_i2c_mode;
#[doc = "USCI_B0 SPI Mode"]
pub type UsciB0SpiMode = crate::Periph<usci_b0_spi_mode::RegisterBlock, 0x05e0>;
impl core::fmt::Debug for UsciB0SpiMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciB0SpiMode").finish()
}
}
#[doc = "USCI_B0 SPI Mode"]
pub mod usci_b0_spi_mode;
#[doc = "ADC12"]
pub type Adc12 = crate::Periph<adc12::RegisterBlock, 0x0700>;
impl core::fmt::Debug for Adc12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Adc12").finish()
}
}
#[doc = "ADC12"]
pub mod adc12;
#[doc = "SFR Special Function Registers"]
pub type Sfr = crate::Periph<sfr::RegisterBlock, 0x0100>;
impl core::fmt::Debug for Sfr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sfr").finish()
}
}
#[doc = "SFR Special Function Registers"]
pub mod sfr;
#[doc = "PMM Power Management System"]
pub type Pmm = crate::Periph<pmm::RegisterBlock, 0x0120>;
impl core::fmt::Debug for Pmm {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pmm").finish()
}
}
#[doc = "PMM Power Management System"]
pub mod pmm;
#[doc = "Flash"]
pub type Flash = crate::Periph<flash::RegisterBlock, 0x0140>;
impl core::fmt::Debug for Flash {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Flash").finish()
}
}
#[doc = "Flash"]
pub mod flash;
#[doc = "CRC16"]
pub type Crc16 = crate::Periph<crc16::RegisterBlock, 0x0150>;
impl core::fmt::Debug for Crc16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc16").finish()
}
}
#[doc = "CRC16"]
pub mod crc16;
#[doc = "RC RAM Control Module"]
pub type Rc = crate::Periph<rc::RegisterBlock, 0x0158>;
impl core::fmt::Debug for Rc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rc").finish()
}
}
#[doc = "RC RAM Control Module"]
pub mod rc;
#[doc = "Watchdog Timer"]
pub type WatchdogTimer = crate::Periph<watchdog_timer::RegisterBlock, 0x015c>;
impl core::fmt::Debug for WatchdogTimer {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WatchdogTimer").finish()
}
}
#[doc = "Watchdog Timer"]
pub mod watchdog_timer;
#[doc = "UCS Unified System Clock"]
pub type Ucs = crate::Periph<ucs::RegisterBlock, 0x0160>;
impl core::fmt::Debug for Ucs {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ucs").finish()
}
}
#[doc = "UCS Unified System Clock"]
pub mod ucs;
#[doc = "SYS System Module"]
pub type Sys = crate::Periph<sys::RegisterBlock, 0x0180>;
impl core::fmt::Debug for Sys {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sys").finish()
}
}
#[doc = "SYS System Module"]
pub mod sys;
#[doc = "Shared Reference"]
pub type SharedReference = crate::Periph<shared_reference::RegisterBlock, 0x01b0>;
impl core::fmt::Debug for SharedReference {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SharedReference").finish()
}
}
#[doc = "Shared Reference"]
pub mod shared_reference;
#[doc = "Port Mapping Control"]
pub type PortMappingControl = crate::Periph<port_mapping_control::RegisterBlock, 0x01c0>;
impl core::fmt::Debug for PortMappingControl {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortMappingControl").finish()
}
}
#[doc = "Port Mapping Control"]
pub mod port_mapping_control;
#[doc = "Port J"]
pub type PortJ = crate::Periph<port_j::RegisterBlock, 0x0320>;
impl core::fmt::Debug for PortJ {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortJ").finish()
}
}
#[doc = "Port J"]
pub mod port_j;
#[doc = "Timer A5"]
pub type Timer0A5 = crate::Periph<timer0_a5::RegisterBlock, 0x0340>;
impl core::fmt::Debug for Timer0A5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer0A5").finish()
}
}
#[doc = "Timer A5"]
pub mod timer0_a5;
#[doc = "Timer A3"]
pub type Timer1A3 = crate::Periph<timer1_a3::RegisterBlock, 0x0380>;
impl core::fmt::Debug for Timer1A3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer1A3").finish()
}
}
#[doc = "Timer A3"]
pub mod timer1_a3;
#[doc = "MPY 16 Multiplier 16 Bit Mode"]
pub type Mpy16 = crate::Periph<mpy_16::RegisterBlock, 0x04c0>;
impl core::fmt::Debug for Mpy16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpy16").finish()
}
}
#[doc = "MPY 16 Multiplier 16 Bit Mode"]
pub mod mpy_16;
#[doc = "MPY 32 Multiplier 32 Bit Mode"]
pub type Mpy32 = crate::Periph<mpy_32::RegisterBlock, 0x04d0>;
impl core::fmt::Debug for Mpy32 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpy32").finish()
}
}
#[doc = "MPY 32 Multiplier 32 Bit Mode"]
pub mod mpy_32;
#[doc = "DMA"]
pub type Dma = crate::Periph<dma::RegisterBlock, 0x0500>;
impl core::fmt::Debug for Dma {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dma").finish()
}
}
#[doc = "DMA"]
pub mod dma;
#[doc = "Comparator B"]
pub type ComparatorB = crate::Periph<comparator_b::RegisterBlock, 0x08c0>;
impl core::fmt::Debug for ComparatorB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ComparatorB").finish()
}
}
#[doc = "Comparator B"]
pub mod comparator_b;
#[doc = "AES Accelerator"]
pub type AesAccelerator = crate::Periph<aes_accelerator::RegisterBlock, 0x09c0>;
impl core::fmt::Debug for AesAccelerator {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AesAccelerator").finish()
}
}
#[doc = "AES Accelerator"]
pub mod aes_accelerator;
#[doc = "CC1101 Radio Interface"]
pub type Cc1101RadioInterface = crate::Periph<cc1101_radio_interface::RegisterBlock, 0x0f00>;
impl core::fmt::Debug for Cc1101RadioInterface {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cc1101RadioInterface").finish()
}
}
#[doc = "CC1101 Radio Interface"]
pub mod cc1101_radio_interface;
#[unsafe(no_mangle)]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "PORT_MAPPING_PORT_1"]
pub port_mapping_port_1: PortMappingPort1,
#[doc = "PORT_MAPPING_PORT_2"]
pub port_mapping_port_2: PortMappingPort2,
#[doc = "PORT_MAPPING_PORT_3"]
pub port_mapping_port_3: PortMappingPort3,
#[doc = "PORT_1_2"]
pub port_1_2: Port1_2,
#[doc = "PORT_3"]
pub port_3: Port3,
#[doc = "PORT_5"]
pub port_5: Port5,
#[doc = "RTC"]
pub rtc: Rtc,
#[doc = "USCI_A0_UART_MODE"]
pub usci_a0_uart_mode: UsciA0UartMode,
#[doc = "USCI_A0_SPI_MODE"]
pub usci_a0_spi_mode: UsciA0SpiMode,
#[doc = "USCI_B0_I2C_MODE"]
pub usci_b0_i2c_mode: UsciB0I2cMode,
#[doc = "USCI_B0_SPI_MODE"]
pub usci_b0_spi_mode: UsciB0SpiMode,
#[doc = "ADC12"]
pub adc12: Adc12,
#[doc = "SFR"]
pub sfr: Sfr,
#[doc = "PMM"]
pub pmm: Pmm,
#[doc = "FLASH"]
pub flash: Flash,
#[doc = "CRC16"]
pub crc16: Crc16,
#[doc = "RC"]
pub rc: Rc,
#[doc = "WATCHDOG_TIMER"]
pub watchdog_timer: WatchdogTimer,
#[doc = "UCS"]
pub ucs: Ucs,
#[doc = "SYS"]
pub sys: Sys,
#[doc = "SHARED_REFERENCE"]
pub shared_reference: SharedReference,
#[doc = "PORT_MAPPING_CONTROL"]
pub port_mapping_control: PortMappingControl,
#[doc = "PORT_J"]
pub port_j: PortJ,
#[doc = "TIMER0_A5"]
pub timer0_a5: Timer0A5,
#[doc = "TIMER1_A3"]
pub timer1_a3: Timer1A3,
#[doc = "MPY_16"]
pub mpy_16: Mpy16,
#[doc = "MPY_32"]
pub mpy_32: Mpy32,
#[doc = "DMA"]
pub dma: Dma,
#[doc = "COMPARATOR_B"]
pub comparator_b: ComparatorB,
#[doc = "AES_ACCELERATOR"]
pub aes_accelerator: AesAccelerator,
#[doc = "CC1101_RADIO_INTERFACE"]
pub cc1101_radio_interface: Cc1101RadioInterface,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
port_mapping_port_1: PortMappingPort1::steal(),
port_mapping_port_2: PortMappingPort2::steal(),
port_mapping_port_3: PortMappingPort3::steal(),
port_1_2: Port1_2::steal(),
port_3: Port3::steal(),
port_5: Port5::steal(),
rtc: Rtc::steal(),
usci_a0_uart_mode: UsciA0UartMode::steal(),
usci_a0_spi_mode: UsciA0SpiMode::steal(),
usci_b0_i2c_mode: UsciB0I2cMode::steal(),
usci_b0_spi_mode: UsciB0SpiMode::steal(),
adc12: Adc12::steal(),
sfr: Sfr::steal(),
pmm: Pmm::steal(),
flash: Flash::steal(),
crc16: Crc16::steal(),
rc: Rc::steal(),
watchdog_timer: WatchdogTimer::steal(),
ucs: Ucs::steal(),
sys: Sys::steal(),
shared_reference: SharedReference::steal(),
port_mapping_control: PortMappingControl::steal(),
port_j: PortJ::steal(),
timer0_a5: Timer0A5::steal(),
timer1_a3: Timer1A3::steal(),
mpy_16: Mpy16::steal(),
mpy_32: Mpy32::steal(),
dma: Dma::steal(),
comparator_b: ComparatorB::steal(),
aes_accelerator: AesAccelerator::steal(),
cc1101_radio_interface: Cc1101RadioInterface::steal(),
}
}
}