cc430f5137 0.1.0

Peripheral access API for CC430F5137 microcontroller
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#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
    dmactl0: Dmactl0,
    dmactl1: Dmactl1,
    dmactl2: Dmactl2,
    dmactl3: Dmactl3,
    dmactl4: Dmactl4,
    _reserved5: [u8; 0x04],
    dmaiv: Dmaiv,
    dma0ctl: Dma0ctl,
    dma0sa: Dma0sa,
    dma0da: Dma0da,
    dma0sz: Dma0sz,
    _reserved10: [u8; 0x04],
    dma1ctl: Dma1ctl,
    dma1sa: Dma1sa,
    dma1da: Dma1da,
    dma1sz: Dma1sz,
    _reserved14: [u8; 0x04],
    dma2ctl: Dma2ctl,
    dma2sa: Dma2sa,
    dma2da: Dma2da,
    dma2sz: Dma2sz,
}
impl RegisterBlock {
    #[doc = "0x00 - DMA Module Control 0"]
    #[inline(always)]
    pub const fn dmactl0(&self) -> &Dmactl0 {
        &self.dmactl0
    }
    #[doc = "0x02 - DMA Module Control 1"]
    #[inline(always)]
    pub const fn dmactl1(&self) -> &Dmactl1 {
        &self.dmactl1
    }
    #[doc = "0x04 - DMA Module Control 2"]
    #[inline(always)]
    pub const fn dmactl2(&self) -> &Dmactl2 {
        &self.dmactl2
    }
    #[doc = "0x06 - DMA Module Control 3"]
    #[inline(always)]
    pub const fn dmactl3(&self) -> &Dmactl3 {
        &self.dmactl3
    }
    #[doc = "0x08 - DMA Module Control 4"]
    #[inline(always)]
    pub const fn dmactl4(&self) -> &Dmactl4 {
        &self.dmactl4
    }
    #[doc = "0x0e - DMA Interrupt Vector Word"]
    #[inline(always)]
    pub const fn dmaiv(&self) -> &Dmaiv {
        &self.dmaiv
    }
    #[doc = "0x10 - DMA Channel 0 Control"]
    #[inline(always)]
    pub const fn dma0ctl(&self) -> &Dma0ctl {
        &self.dma0ctl
    }
    #[doc = "0x12 - DMA Channel 0 Source Address"]
    #[inline(always)]
    pub const fn dma0sa(&self) -> &Dma0sa {
        &self.dma0sa
    }
    #[doc = "0x16 - DMA Channel 0 Destination Address"]
    #[inline(always)]
    pub const fn dma0da(&self) -> &Dma0da {
        &self.dma0da
    }
    #[doc = "0x1a - DMA Channel 0 Transfer Size"]
    #[inline(always)]
    pub const fn dma0sz(&self) -> &Dma0sz {
        &self.dma0sz
    }
    #[doc = "0x20 - DMA Channel 1 Control"]
    #[inline(always)]
    pub const fn dma1ctl(&self) -> &Dma1ctl {
        &self.dma1ctl
    }
    #[doc = "0x22 - DMA Channel 1 Source Address"]
    #[inline(always)]
    pub const fn dma1sa(&self) -> &Dma1sa {
        &self.dma1sa
    }
    #[doc = "0x26 - DMA Channel 1 Destination Address"]
    #[inline(always)]
    pub const fn dma1da(&self) -> &Dma1da {
        &self.dma1da
    }
    #[doc = "0x2a - DMA Channel 1 Transfer Size"]
    #[inline(always)]
    pub const fn dma1sz(&self) -> &Dma1sz {
        &self.dma1sz
    }
    #[doc = "0x30 - DMA Channel 2 Control"]
    #[inline(always)]
    pub const fn dma2ctl(&self) -> &Dma2ctl {
        &self.dma2ctl
    }
    #[doc = "0x32 - DMA Channel 2 Source Address"]
    #[inline(always)]
    pub const fn dma2sa(&self) -> &Dma2sa {
        &self.dma2sa
    }
    #[doc = "0x36 - DMA Channel 2 Destination Address"]
    #[inline(always)]
    pub const fn dma2da(&self) -> &Dma2da {
        &self.dma2da
    }
    #[doc = "0x3a - DMA Channel 2 Transfer Size"]
    #[inline(always)]
    pub const fn dma2sz(&self) -> &Dma2sz {
        &self.dma2sz
    }
}
#[doc = "DMACTL0 (rw) register accessor: DMA Module Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl0`] module"]
#[doc(alias = "DMACTL0")]
pub type Dmactl0 = crate::Reg<dmactl0::Dmactl0Spec>;
#[doc = "DMA Module Control 0"]
pub mod dmactl0;
#[doc = "DMACTL1 (rw) register accessor: DMA Module Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl1`] module"]
#[doc(alias = "DMACTL1")]
pub type Dmactl1 = crate::Reg<dmactl1::Dmactl1Spec>;
#[doc = "DMA Module Control 1"]
pub mod dmactl1;
#[doc = "DMACTL2 (rw) register accessor: DMA Module Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl2`] module"]
#[doc(alias = "DMACTL2")]
pub type Dmactl2 = crate::Reg<dmactl2::Dmactl2Spec>;
#[doc = "DMA Module Control 2"]
pub mod dmactl2;
#[doc = "DMACTL3 (rw) register accessor: DMA Module Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl3`] module"]
#[doc(alias = "DMACTL3")]
pub type Dmactl3 = crate::Reg<dmactl3::Dmactl3Spec>;
#[doc = "DMA Module Control 3"]
pub mod dmactl3;
#[doc = "DMACTL4 (rw) register accessor: DMA Module Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl4`] module"]
#[doc(alias = "DMACTL4")]
pub type Dmactl4 = crate::Reg<dmactl4::Dmactl4Spec>;
#[doc = "DMA Module Control 4"]
pub mod dmactl4;
#[doc = "DMAIV (rw) register accessor: DMA Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaiv`] module"]
#[doc(alias = "DMAIV")]
pub type Dmaiv = crate::Reg<dmaiv::DmaivSpec>;
#[doc = "DMA Interrupt Vector Word"]
pub mod dmaiv;
#[doc = "DMA0CTL (rw) register accessor: DMA Channel 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0ctl`] module"]
#[doc(alias = "DMA0CTL")]
pub type Dma0ctl = crate::Reg<dma0ctl::Dma0ctlSpec>;
#[doc = "DMA Channel 0 Control"]
pub mod dma0ctl;
#[doc = "DMA0SZ (rw) register accessor: DMA Channel 0 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0sz`] module"]
#[doc(alias = "DMA0SZ")]
pub type Dma0sz = crate::Reg<dma0sz::Dma0szSpec>;
#[doc = "DMA Channel 0 Transfer Size"]
pub mod dma0sz;
#[doc = "DMA1CTL (rw) register accessor: DMA Channel 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1ctl`] module"]
#[doc(alias = "DMA1CTL")]
pub type Dma1ctl = crate::Reg<dma1ctl::Dma1ctlSpec>;
#[doc = "DMA Channel 1 Control"]
pub mod dma1ctl;
#[doc = "DMA1SZ (rw) register accessor: DMA Channel 1 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1sz`] module"]
#[doc(alias = "DMA1SZ")]
pub type Dma1sz = crate::Reg<dma1sz::Dma1szSpec>;
#[doc = "DMA Channel 1 Transfer Size"]
pub mod dma1sz;
#[doc = "DMA2CTL (rw) register accessor: DMA Channel 2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2ctl`] module"]
#[doc(alias = "DMA2CTL")]
pub type Dma2ctl = crate::Reg<dma2ctl::Dma2ctlSpec>;
#[doc = "DMA Channel 2 Control"]
pub mod dma2ctl;
#[doc = "DMA2SZ (rw) register accessor: DMA Channel 2 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2sz`] module"]
#[doc(alias = "DMA2SZ")]
pub type Dma2sz = crate::Reg<dma2sz::Dma2szSpec>;
#[doc = "DMA Channel 2 Transfer Size"]
pub mod dma2sz;
#[doc = "DMA0SA (rw) register accessor: DMA Channel 0 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0sa`] module"]
#[doc(alias = "DMA0SA")]
pub type Dma0sa = crate::Reg<dma0sa::Dma0saSpec>;
#[doc = "DMA Channel 0 Source Address"]
pub mod dma0sa;
#[doc = "DMA0DA (rw) register accessor: DMA Channel 0 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0da`] module"]
#[doc(alias = "DMA0DA")]
pub type Dma0da = crate::Reg<dma0da::Dma0daSpec>;
#[doc = "DMA Channel 0 Destination Address"]
pub mod dma0da;
#[doc = "DMA1SA (rw) register accessor: DMA Channel 1 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1sa`] module"]
#[doc(alias = "DMA1SA")]
pub type Dma1sa = crate::Reg<dma1sa::Dma1saSpec>;
#[doc = "DMA Channel 1 Source Address"]
pub mod dma1sa;
#[doc = "DMA1DA (rw) register accessor: DMA Channel 1 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1da`] module"]
#[doc(alias = "DMA1DA")]
pub type Dma1da = crate::Reg<dma1da::Dma1daSpec>;
#[doc = "DMA Channel 1 Destination Address"]
pub mod dma1da;
#[doc = "DMA2SA (rw) register accessor: DMA Channel 2 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2sa`] module"]
#[doc(alias = "DMA2SA")]
pub type Dma2sa = crate::Reg<dma2sa::Dma2saSpec>;
#[doc = "DMA Channel 2 Source Address"]
pub mod dma2sa;
#[doc = "DMA2DA (rw) register accessor: DMA Channel 2 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2da`] module"]
#[doc(alias = "DMA2DA")]
pub type Dma2da = crate::Reg<dma2da::Dma2daSpec>;
#[doc = "DMA Channel 2 Destination Address"]
pub mod dma2da;