#[doc = "Register `NVIC_ICPR0` reader"]
pub type R = crate::R<NvicIcpr0Spec>;
#[doc = "Register `NVIC_ICPR0` writer"]
pub type W = crate::W<NvicIcpr0Spec>;
#[doc = "Field `CLRPEND0` reader - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state."]
pub type Clrpend0R = crate::BitReader;
#[doc = "Field `CLRPEND0` writer - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state."]
pub type Clrpend0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND1` reader - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state."]
pub type Clrpend1R = crate::BitReader;
#[doc = "Field `CLRPEND1` writer - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state."]
pub type Clrpend1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND2` reader - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state."]
pub type Clrpend2R = crate::BitReader;
#[doc = "Field `CLRPEND2` writer - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state."]
pub type Clrpend2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND3` reader - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state."]
pub type Clrpend3R = crate::BitReader;
#[doc = "Field `CLRPEND3` writer - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state."]
pub type Clrpend3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND4` reader - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state."]
pub type Clrpend4R = crate::BitReader;
#[doc = "Field `CLRPEND4` writer - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state."]
pub type Clrpend4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND5` reader - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state."]
pub type Clrpend5R = crate::BitReader;
#[doc = "Field `CLRPEND5` writer - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state."]
pub type Clrpend5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND6` reader - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state."]
pub type Clrpend6R = crate::BitReader;
#[doc = "Field `CLRPEND6` writer - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state."]
pub type Clrpend6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND7` reader - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state."]
pub type Clrpend7R = crate::BitReader;
#[doc = "Field `CLRPEND7` writer - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state."]
pub type Clrpend7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND8` reader - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state."]
pub type Clrpend8R = crate::BitReader;
#[doc = "Field `CLRPEND8` writer - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state."]
pub type Clrpend8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND9` reader - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state."]
pub type Clrpend9R = crate::BitReader;
#[doc = "Field `CLRPEND9` writer - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state."]
pub type Clrpend9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND10` reader - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state."]
pub type Clrpend10R = crate::BitReader;
#[doc = "Field `CLRPEND10` writer - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state."]
pub type Clrpend10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND11` reader - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state."]
pub type Clrpend11R = crate::BitReader;
#[doc = "Field `CLRPEND11` writer - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state."]
pub type Clrpend11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND12` reader - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state."]
pub type Clrpend12R = crate::BitReader;
#[doc = "Field `CLRPEND12` writer - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state."]
pub type Clrpend12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND13` reader - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state."]
pub type Clrpend13R = crate::BitReader;
#[doc = "Field `CLRPEND13` writer - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state."]
pub type Clrpend13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND14` reader - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state."]
pub type Clrpend14R = crate::BitReader;
#[doc = "Field `CLRPEND14` writer - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state."]
pub type Clrpend14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND15` reader - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state."]
pub type Clrpend15R = crate::BitReader;
#[doc = "Field `CLRPEND15` writer - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state."]
pub type Clrpend15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND16` reader - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state."]
pub type Clrpend16R = crate::BitReader;
#[doc = "Field `CLRPEND16` writer - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state."]
pub type Clrpend16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND17` reader - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state."]
pub type Clrpend17R = crate::BitReader;
#[doc = "Field `CLRPEND17` writer - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state."]
pub type Clrpend17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND18` reader - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state."]
pub type Clrpend18R = crate::BitReader;
#[doc = "Field `CLRPEND18` writer - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state."]
pub type Clrpend18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND19` reader - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state."]
pub type Clrpend19R = crate::BitReader;
#[doc = "Field `CLRPEND19` writer - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state."]
pub type Clrpend19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND20` reader - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state."]
pub type Clrpend20R = crate::BitReader;
#[doc = "Field `CLRPEND20` writer - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state."]
pub type Clrpend20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND21` reader - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state."]
pub type Clrpend21R = crate::BitReader;
#[doc = "Field `CLRPEND21` writer - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state."]
pub type Clrpend21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND22` reader - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state."]
pub type Clrpend22R = crate::BitReader;
#[doc = "Field `CLRPEND22` writer - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state."]
pub type Clrpend22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND23` reader - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state."]
pub type Clrpend23R = crate::BitReader;
#[doc = "Field `CLRPEND23` writer - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state."]
pub type Clrpend23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND24` reader - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state."]
pub type Clrpend24R = crate::BitReader;
#[doc = "Field `CLRPEND24` writer - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state."]
pub type Clrpend24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND25` reader - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state."]
pub type Clrpend25R = crate::BitReader;
#[doc = "Field `CLRPEND25` writer - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state."]
pub type Clrpend25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND26` reader - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state."]
pub type Clrpend26R = crate::BitReader;
#[doc = "Field `CLRPEND26` writer - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state."]
pub type Clrpend26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND27` reader - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state."]
pub type Clrpend27R = crate::BitReader;
#[doc = "Field `CLRPEND27` writer - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state."]
pub type Clrpend27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND28` reader - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state."]
pub type Clrpend28R = crate::BitReader;
#[doc = "Field `CLRPEND28` writer - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state."]
pub type Clrpend28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND29` reader - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state."]
pub type Clrpend29R = crate::BitReader;
#[doc = "Field `CLRPEND29` writer - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state."]
pub type Clrpend29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND30` reader - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state."]
pub type Clrpend30R = crate::BitReader;
#[doc = "Field `CLRPEND30` writer - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state."]
pub type Clrpend30W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRPEND31` reader - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state."]
pub type Clrpend31R = crate::BitReader;
#[doc = "Field `CLRPEND31` writer - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state."]
pub type Clrpend31W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend0(&self) -> Clrpend0R {
Clrpend0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend1(&self) -> Clrpend1R {
Clrpend1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend2(&self) -> Clrpend2R {
Clrpend2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend3(&self) -> Clrpend3R {
Clrpend3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend4(&self) -> Clrpend4R {
Clrpend4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend5(&self) -> Clrpend5R {
Clrpend5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend6(&self) -> Clrpend6R {
Clrpend6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend7(&self) -> Clrpend7R {
Clrpend7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend8(&self) -> Clrpend8R {
Clrpend8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend9(&self) -> Clrpend9R {
Clrpend9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend10(&self) -> Clrpend10R {
Clrpend10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend11(&self) -> Clrpend11R {
Clrpend11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend12(&self) -> Clrpend12R {
Clrpend12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend13(&self) -> Clrpend13R {
Clrpend13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend14(&self) -> Clrpend14R {
Clrpend14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend15(&self) -> Clrpend15R {
Clrpend15R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend16(&self) -> Clrpend16R {
Clrpend16R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend17(&self) -> Clrpend17R {
Clrpend17R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend18(&self) -> Clrpend18R {
Clrpend18R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend19(&self) -> Clrpend19R {
Clrpend19R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend20(&self) -> Clrpend20R {
Clrpend20R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend21(&self) -> Clrpend21R {
Clrpend21R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend22(&self) -> Clrpend22R {
Clrpend22R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend23(&self) -> Clrpend23R {
Clrpend23R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend24(&self) -> Clrpend24R {
Clrpend24R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend25(&self) -> Clrpend25R {
Clrpend25R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend26(&self) -> Clrpend26R {
Clrpend26R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend27(&self) -> Clrpend27R {
Clrpend27R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend28(&self) -> Clrpend28R {
Clrpend28R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend29(&self) -> Clrpend29R {
Clrpend29R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend30(&self) -> Clrpend30R {
Clrpend30R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state."]
#[inline(always)]
pub fn clrpend31(&self) -> Clrpend31R {
Clrpend31R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend0(&mut self) -> Clrpend0W<NvicIcpr0Spec> {
Clrpend0W::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend1(&mut self) -> Clrpend1W<NvicIcpr0Spec> {
Clrpend1W::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend2(&mut self) -> Clrpend2W<NvicIcpr0Spec> {
Clrpend2W::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend3(&mut self) -> Clrpend3W<NvicIcpr0Spec> {
Clrpend3W::new(self, 3)
}
#[doc = "Bit 4 - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend4(&mut self) -> Clrpend4W<NvicIcpr0Spec> {
Clrpend4W::new(self, 4)
}
#[doc = "Bit 5 - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend5(&mut self) -> Clrpend5W<NvicIcpr0Spec> {
Clrpend5W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend6(&mut self) -> Clrpend6W<NvicIcpr0Spec> {
Clrpend6W::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend7(&mut self) -> Clrpend7W<NvicIcpr0Spec> {
Clrpend7W::new(self, 7)
}
#[doc = "Bit 8 - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend8(&mut self) -> Clrpend8W<NvicIcpr0Spec> {
Clrpend8W::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend9(&mut self) -> Clrpend9W<NvicIcpr0Spec> {
Clrpend9W::new(self, 9)
}
#[doc = "Bit 10 - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend10(&mut self) -> Clrpend10W<NvicIcpr0Spec> {
Clrpend10W::new(self, 10)
}
#[doc = "Bit 11 - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend11(&mut self) -> Clrpend11W<NvicIcpr0Spec> {
Clrpend11W::new(self, 11)
}
#[doc = "Bit 12 - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend12(&mut self) -> Clrpend12W<NvicIcpr0Spec> {
Clrpend12W::new(self, 12)
}
#[doc = "Bit 13 - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend13(&mut self) -> Clrpend13W<NvicIcpr0Spec> {
Clrpend13W::new(self, 13)
}
#[doc = "Bit 14 - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend14(&mut self) -> Clrpend14W<NvicIcpr0Spec> {
Clrpend14W::new(self, 14)
}
#[doc = "Bit 15 - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend15(&mut self) -> Clrpend15W<NvicIcpr0Spec> {
Clrpend15W::new(self, 15)
}
#[doc = "Bit 16 - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend16(&mut self) -> Clrpend16W<NvicIcpr0Spec> {
Clrpend16W::new(self, 16)
}
#[doc = "Bit 17 - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend17(&mut self) -> Clrpend17W<NvicIcpr0Spec> {
Clrpend17W::new(self, 17)
}
#[doc = "Bit 18 - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend18(&mut self) -> Clrpend18W<NvicIcpr0Spec> {
Clrpend18W::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend19(&mut self) -> Clrpend19W<NvicIcpr0Spec> {
Clrpend19W::new(self, 19)
}
#[doc = "Bit 20 - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend20(&mut self) -> Clrpend20W<NvicIcpr0Spec> {
Clrpend20W::new(self, 20)
}
#[doc = "Bit 21 - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend21(&mut self) -> Clrpend21W<NvicIcpr0Spec> {
Clrpend21W::new(self, 21)
}
#[doc = "Bit 22 - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend22(&mut self) -> Clrpend22W<NvicIcpr0Spec> {
Clrpend22W::new(self, 22)
}
#[doc = "Bit 23 - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend23(&mut self) -> Clrpend23W<NvicIcpr0Spec> {
Clrpend23W::new(self, 23)
}
#[doc = "Bit 24 - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend24(&mut self) -> Clrpend24W<NvicIcpr0Spec> {
Clrpend24W::new(self, 24)
}
#[doc = "Bit 25 - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend25(&mut self) -> Clrpend25W<NvicIcpr0Spec> {
Clrpend25W::new(self, 25)
}
#[doc = "Bit 26 - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend26(&mut self) -> Clrpend26W<NvicIcpr0Spec> {
Clrpend26W::new(self, 26)
}
#[doc = "Bit 27 - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend27(&mut self) -> Clrpend27W<NvicIcpr0Spec> {
Clrpend27W::new(self, 27)
}
#[doc = "Bit 28 - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend28(&mut self) -> Clrpend28W<NvicIcpr0Spec> {
Clrpend28W::new(self, 28)
}
#[doc = "Bit 29 - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend29(&mut self) -> Clrpend29W<NvicIcpr0Spec> {
Clrpend29W::new(self, 29)
}
#[doc = "Bit 30 - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend30(&mut self) -> Clrpend30W<NvicIcpr0Spec> {
Clrpend30W::new(self, 30)
}
#[doc = "Bit 31 - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state."]
#[inline(always)]
#[must_use]
pub fn clrpend31(&mut self) -> Clrpend31W<NvicIcpr0Spec> {
Clrpend31W::new(self, 31)
}
}
#[doc = "Irq 0 to 31 Clear Pending This register is used to clear pending interrupts and determine which interrupts are currently pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nvic_icpr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icpr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NvicIcpr0Spec;
impl crate::RegisterSpec for NvicIcpr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`nvic_icpr0::R`](R) reader structure"]
impl crate::Readable for NvicIcpr0Spec {}
#[doc = "`write(|w| ..)` method takes [`nvic_icpr0::W`](W) writer structure"]
impl crate::Writable for NvicIcpr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NVIC_ICPR0 to value 0"]
impl crate::Resettable for NvicIcpr0Spec {
const RESET_VALUE: u32 = 0;
}