#[doc = "Register `NVIC_ICER0` reader"]
pub type R = crate::R<NvicIcer0Spec>;
#[doc = "Register `NVIC_ICER0` writer"]
pub type W = crate::W<NvicIcer0Spec>;
#[doc = "Field `CLRENA0` reader - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state."]
pub type Clrena0R = crate::BitReader;
#[doc = "Field `CLRENA0` writer - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state."]
pub type Clrena0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA1` reader - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state."]
pub type Clrena1R = crate::BitReader;
#[doc = "Field `CLRENA1` writer - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state."]
pub type Clrena1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA2` reader - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state."]
pub type Clrena2R = crate::BitReader;
#[doc = "Field `CLRENA2` writer - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state."]
pub type Clrena2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA3` reader - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state."]
pub type Clrena3R = crate::BitReader;
#[doc = "Field `CLRENA3` writer - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state."]
pub type Clrena3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA4` reader - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state."]
pub type Clrena4R = crate::BitReader;
#[doc = "Field `CLRENA4` writer - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state."]
pub type Clrena4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA5` reader - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state."]
pub type Clrena5R = crate::BitReader;
#[doc = "Field `CLRENA5` writer - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state."]
pub type Clrena5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA6` reader - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state."]
pub type Clrena6R = crate::BitReader;
#[doc = "Field `CLRENA6` writer - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state."]
pub type Clrena6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA7` reader - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state."]
pub type Clrena7R = crate::BitReader;
#[doc = "Field `CLRENA7` writer - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state."]
pub type Clrena7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA8` reader - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state."]
pub type Clrena8R = crate::BitReader;
#[doc = "Field `CLRENA8` writer - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state."]
pub type Clrena8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA9` reader - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state."]
pub type Clrena9R = crate::BitReader;
#[doc = "Field `CLRENA9` writer - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state."]
pub type Clrena9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA10` reader - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state."]
pub type Clrena10R = crate::BitReader;
#[doc = "Field `CLRENA10` writer - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state."]
pub type Clrena10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA11` reader - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state."]
pub type Clrena11R = crate::BitReader;
#[doc = "Field `CLRENA11` writer - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state."]
pub type Clrena11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA12` reader - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state."]
pub type Clrena12R = crate::BitReader;
#[doc = "Field `CLRENA12` writer - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state."]
pub type Clrena12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA13` reader - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state."]
pub type Clrena13R = crate::BitReader;
#[doc = "Field `CLRENA13` writer - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state."]
pub type Clrena13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA14` reader - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state."]
pub type Clrena14R = crate::BitReader;
#[doc = "Field `CLRENA14` writer - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state."]
pub type Clrena14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA15` reader - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state."]
pub type Clrena15R = crate::BitReader;
#[doc = "Field `CLRENA15` writer - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state."]
pub type Clrena15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA16` reader - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state."]
pub type Clrena16R = crate::BitReader;
#[doc = "Field `CLRENA16` writer - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state."]
pub type Clrena16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA17` reader - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state."]
pub type Clrena17R = crate::BitReader;
#[doc = "Field `CLRENA17` writer - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state."]
pub type Clrena17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA18` reader - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state."]
pub type Clrena18R = crate::BitReader;
#[doc = "Field `CLRENA18` writer - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state."]
pub type Clrena18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA19` reader - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state."]
pub type Clrena19R = crate::BitReader;
#[doc = "Field `CLRENA19` writer - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state."]
pub type Clrena19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA20` reader - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state."]
pub type Clrena20R = crate::BitReader;
#[doc = "Field `CLRENA20` writer - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state."]
pub type Clrena20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA21` reader - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state."]
pub type Clrena21R = crate::BitReader;
#[doc = "Field `CLRENA21` writer - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state."]
pub type Clrena21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA22` reader - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state."]
pub type Clrena22R = crate::BitReader;
#[doc = "Field `CLRENA22` writer - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state."]
pub type Clrena22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA23` reader - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state."]
pub type Clrena23R = crate::BitReader;
#[doc = "Field `CLRENA23` writer - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state."]
pub type Clrena23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA24` reader - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state."]
pub type Clrena24R = crate::BitReader;
#[doc = "Field `CLRENA24` writer - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state."]
pub type Clrena24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA25` reader - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state."]
pub type Clrena25R = crate::BitReader;
#[doc = "Field `CLRENA25` writer - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state."]
pub type Clrena25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA26` reader - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state."]
pub type Clrena26R = crate::BitReader;
#[doc = "Field `CLRENA26` writer - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state."]
pub type Clrena26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA27` reader - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state."]
pub type Clrena27R = crate::BitReader;
#[doc = "Field `CLRENA27` writer - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state."]
pub type Clrena27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA28` reader - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state."]
pub type Clrena28R = crate::BitReader;
#[doc = "Field `CLRENA28` writer - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state."]
pub type Clrena28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA29` reader - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state."]
pub type Clrena29R = crate::BitReader;
#[doc = "Field `CLRENA29` writer - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state."]
pub type Clrena29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA30` reader - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state."]
pub type Clrena30R = crate::BitReader;
#[doc = "Field `CLRENA30` writer - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state."]
pub type Clrena30W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLRENA31` reader - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state."]
pub type Clrena31R = crate::BitReader;
#[doc = "Field `CLRENA31` writer - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state."]
pub type Clrena31W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena0(&self) -> Clrena0R {
Clrena0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena1(&self) -> Clrena1R {
Clrena1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena2(&self) -> Clrena2R {
Clrena2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena3(&self) -> Clrena3R {
Clrena3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena4(&self) -> Clrena4R {
Clrena4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena5(&self) -> Clrena5R {
Clrena5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena6(&self) -> Clrena6R {
Clrena6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena7(&self) -> Clrena7R {
Clrena7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena8(&self) -> Clrena8R {
Clrena8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena9(&self) -> Clrena9R {
Clrena9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena10(&self) -> Clrena10R {
Clrena10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena11(&self) -> Clrena11R {
Clrena11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena12(&self) -> Clrena12R {
Clrena12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena13(&self) -> Clrena13R {
Clrena13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena14(&self) -> Clrena14R {
Clrena14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena15(&self) -> Clrena15R {
Clrena15R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena16(&self) -> Clrena16R {
Clrena16R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena17(&self) -> Clrena17R {
Clrena17R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena18(&self) -> Clrena18R {
Clrena18R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena19(&self) -> Clrena19R {
Clrena19R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena20(&self) -> Clrena20R {
Clrena20R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena21(&self) -> Clrena21R {
Clrena21R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena22(&self) -> Clrena22R {
Clrena22R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena23(&self) -> Clrena23R {
Clrena23R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena24(&self) -> Clrena24R {
Clrena24R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena25(&self) -> Clrena25R {
Clrena25R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena26(&self) -> Clrena26R {
Clrena26R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena27(&self) -> Clrena27R {
Clrena27R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena28(&self) -> Clrena28R {
Clrena28R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena29(&self) -> Clrena29R {
Clrena29R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena30(&self) -> Clrena30R {
Clrena30R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
pub fn clrena31(&self) -> Clrena31R {
Clrena31R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena0(&mut self) -> Clrena0W<NvicIcer0Spec> {
Clrena0W::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena1(&mut self) -> Clrena1W<NvicIcer0Spec> {
Clrena1W::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena2(&mut self) -> Clrena2W<NvicIcer0Spec> {
Clrena2W::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena3(&mut self) -> Clrena3W<NvicIcer0Spec> {
Clrena3W::new(self, 3)
}
#[doc = "Bit 4 - 4:4\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena4(&mut self) -> Clrena4W<NvicIcer0Spec> {
Clrena4W::new(self, 4)
}
#[doc = "Bit 5 - 5:5\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena5(&mut self) -> Clrena5W<NvicIcer0Spec> {
Clrena5W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena6(&mut self) -> Clrena6W<NvicIcer0Spec> {
Clrena6W::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena7(&mut self) -> Clrena7W<NvicIcer0Spec> {
Clrena7W::new(self, 7)
}
#[doc = "Bit 8 - 8:8\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena8(&mut self) -> Clrena8W<NvicIcer0Spec> {
Clrena8W::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena9(&mut self) -> Clrena9W<NvicIcer0Spec> {
Clrena9W::new(self, 9)
}
#[doc = "Bit 10 - 10:10\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena10(&mut self) -> Clrena10W<NvicIcer0Spec> {
Clrena10W::new(self, 10)
}
#[doc = "Bit 11 - 11:11\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena11(&mut self) -> Clrena11W<NvicIcer0Spec> {
Clrena11W::new(self, 11)
}
#[doc = "Bit 12 - 12:12\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena12(&mut self) -> Clrena12W<NvicIcer0Spec> {
Clrena12W::new(self, 12)
}
#[doc = "Bit 13 - 13:13\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena13(&mut self) -> Clrena13W<NvicIcer0Spec> {
Clrena13W::new(self, 13)
}
#[doc = "Bit 14 - 14:14\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena14(&mut self) -> Clrena14W<NvicIcer0Spec> {
Clrena14W::new(self, 14)
}
#[doc = "Bit 15 - 15:15\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena15(&mut self) -> Clrena15W<NvicIcer0Spec> {
Clrena15W::new(self, 15)
}
#[doc = "Bit 16 - 16:16\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena16(&mut self) -> Clrena16W<NvicIcer0Spec> {
Clrena16W::new(self, 16)
}
#[doc = "Bit 17 - 17:17\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena17(&mut self) -> Clrena17W<NvicIcer0Spec> {
Clrena17W::new(self, 17)
}
#[doc = "Bit 18 - 18:18\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena18(&mut self) -> Clrena18W<NvicIcer0Spec> {
Clrena18W::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena19(&mut self) -> Clrena19W<NvicIcer0Spec> {
Clrena19W::new(self, 19)
}
#[doc = "Bit 20 - 20:20\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena20(&mut self) -> Clrena20W<NvicIcer0Spec> {
Clrena20W::new(self, 20)
}
#[doc = "Bit 21 - 21:21\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena21(&mut self) -> Clrena21W<NvicIcer0Spec> {
Clrena21W::new(self, 21)
}
#[doc = "Bit 22 - 22:22\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena22(&mut self) -> Clrena22W<NvicIcer0Spec> {
Clrena22W::new(self, 22)
}
#[doc = "Bit 23 - 23:23\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena23(&mut self) -> Clrena23W<NvicIcer0Spec> {
Clrena23W::new(self, 23)
}
#[doc = "Bit 24 - 24:24\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena24(&mut self) -> Clrena24W<NvicIcer0Spec> {
Clrena24W::new(self, 24)
}
#[doc = "Bit 25 - 25:25\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena25(&mut self) -> Clrena25W<NvicIcer0Spec> {
Clrena25W::new(self, 25)
}
#[doc = "Bit 26 - 26:26\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena26(&mut self) -> Clrena26W<NvicIcer0Spec> {
Clrena26W::new(self, 26)
}
#[doc = "Bit 27 - 27:27\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena27(&mut self) -> Clrena27W<NvicIcer0Spec> {
Clrena27W::new(self, 27)
}
#[doc = "Bit 28 - 28:28\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena28(&mut self) -> Clrena28W<NvicIcer0Spec> {
Clrena28W::new(self, 28)
}
#[doc = "Bit 29 - 29:29\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena29(&mut self) -> Clrena29W<NvicIcer0Spec> {
Clrena29W::new(self, 29)
}
#[doc = "Bit 30 - 30:30\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena30(&mut self) -> Clrena30W<NvicIcer0Spec> {
Clrena30W::new(self, 30)
}
#[doc = "Bit 31 - 31:31\\]
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state."]
#[inline(always)]
#[must_use]
pub fn clrena31(&mut self) -> Clrena31W<NvicIcer0Spec> {
Clrena31W::new(self, 31)
}
}
#[doc = "Irq 0 to 31 Clear Enable This register is used to disable interrupts and determine which interrupts are currently enabled.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nvic_icer0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_icer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NvicIcer0Spec;
impl crate::RegisterSpec for NvicIcer0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`nvic_icer0::R`](R) reader structure"]
impl crate::Readable for NvicIcer0Spec {}
#[doc = "`write(|w| ..)` method takes [`nvic_icer0::W`](W) writer structure"]
impl crate::Writable for NvicIcer0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NVIC_ICER0 to value 0"]
impl crate::Resettable for NvicIcer0Spec {
const RESET_VALUE: u32 = 0;
}