#[doc = "Register `PRECTL` reader"]
pub type R = crate::R<PrectlSpec>;
#[doc = "Register `PRECTL` writer"]
pub type W = crate::W<PrectlSpec>;
#[doc = "4:0\\]
Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0.\n\nValue on reset: 31"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Src {
#[doc = "31: AUX_EVCTL:EVSTAT1.ADC_IRQ"]
AdcIrq = 31,
#[doc = "30: AUX_EVCTL:EVSTAT1.MCU_EV"]
McuEv = 30,
#[doc = "29: AUX_EVCTL:EVSTAT1.ACLK_REF"]
AclkRef = 29,
#[doc = "28: AUX_EVCTL:EVSTAT1.AUXIO15"]
Auxio15 = 28,
#[doc = "27: AUX_EVCTL:EVSTAT1.AUXIO14"]
Auxio14 = 27,
#[doc = "26: AUX_EVCTL:EVSTAT1.AUXIO13"]
Auxio13 = 26,
#[doc = "25: AUX_EVCTL:EVSTAT1.AUXIO12"]
Auxio12 = 25,
#[doc = "24: AUX_EVCTL:EVSTAT1.AUXIO11"]
Auxio11 = 24,
#[doc = "23: AUX_EVCTL:EVSTAT1.AUXIO10"]
Auxio10 = 23,
#[doc = "22: AUX_EVCTL:EVSTAT1.AUXIO9"]
Auxio9 = 22,
#[doc = "21: AUX_EVCTL:EVSTAT1.AUXIO8"]
Auxio8 = 21,
#[doc = "20: AUX_EVCTL:EVSTAT1.AUXIO7"]
Auxio7 = 20,
#[doc = "19: AUX_EVCTL:EVSTAT1.AUXIO6"]
Auxio6 = 19,
#[doc = "18: AUX_EVCTL:EVSTAT1.AUXIO5"]
Auxio5 = 18,
#[doc = "17: AUX_EVCTL:EVSTAT1.AUXIO4"]
Auxio4 = 17,
#[doc = "16: AUX_EVCTL:EVSTAT1.AUXIO3"]
Auxio3 = 16,
#[doc = "15: AUX_EVCTL:EVSTAT0.AUXIO2"]
Auxio2 = 15,
#[doc = "14: AUX_EVCTL:EVSTAT0.AUXIO1"]
Auxio1 = 14,
#[doc = "13: AUX_EVCTL:EVSTAT0.AUXIO0"]
Auxio0 = 13,
#[doc = "12: AUX_EVCTL:EVSTAT0.AON_PROG_WU"]
AonProgWu = 12,
#[doc = "11: AUX_EVCTL:EVSTAT0.AON_SW"]
AonSw = 11,
#[doc = "10: AUX_EVCTL:EVSTAT0.OBSMUX1"]
Obsmux1 = 10,
#[doc = "9: AUX_EVCTL:EVSTAT0.OBSMUX0"]
Obsmux0 = 9,
#[doc = "8: AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL"]
AdcFifoAlmostFull = 8,
#[doc = "7: AUX_EVCTL:EVSTAT0.ADC_DONE"]
AdcDone = 7,
#[doc = "6: AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE"]
SmphAutotakeDone = 6,
#[doc = "5: AUX_EVCTL:EVSTAT0.TIMER1_EV"]
Timer1Ev = 5,
#[doc = "4: AUX_EVCTL:EVSTAT0.TIMER0_EV"]
Timer0Ev = 4,
#[doc = "3: AUX_ANAIF:ISRCCTL.RESET_N"]
IsrcReset = 3,
#[doc = "2: AUX_EVCTL:EVSTAT0.AUX_COMPB"]
AuxCompb = 2,
#[doc = "1: AUX_EVCTL:EVSTAT0.AUX_COMPA"]
AuxCompa = 1,
#[doc = "0: AUX_EVCTL:EVSTAT0.AON_RTC_CH2"]
AonRtcCh2 = 0,
}
impl From<Src> for u8 {
#[inline(always)]
fn from(variant: Src) -> Self {
variant as _
}
}
impl crate::FieldSpec for Src {
type Ux = u8;
}
impl crate::IsEnum for Src {}
#[doc = "Field `SRC` reader - 4:0\\]
Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0."]
pub type SrcR = crate::FieldReader<Src>;
impl SrcR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Src {
match self.bits {
31 => Src::AdcIrq,
30 => Src::McuEv,
29 => Src::AclkRef,
28 => Src::Auxio15,
27 => Src::Auxio14,
26 => Src::Auxio13,
25 => Src::Auxio12,
24 => Src::Auxio11,
23 => Src::Auxio10,
22 => Src::Auxio9,
21 => Src::Auxio8,
20 => Src::Auxio7,
19 => Src::Auxio6,
18 => Src::Auxio5,
17 => Src::Auxio4,
16 => Src::Auxio3,
15 => Src::Auxio2,
14 => Src::Auxio1,
13 => Src::Auxio0,
12 => Src::AonProgWu,
11 => Src::AonSw,
10 => Src::Obsmux1,
9 => Src::Obsmux0,
8 => Src::AdcFifoAlmostFull,
7 => Src::AdcDone,
6 => Src::SmphAutotakeDone,
5 => Src::Timer1Ev,
4 => Src::Timer0Ev,
3 => Src::IsrcReset,
2 => Src::AuxCompb,
1 => Src::AuxCompa,
0 => Src::AonRtcCh2,
_ => unreachable!(),
}
}
#[doc = "AUX_EVCTL:EVSTAT1.ADC_IRQ"]
#[inline(always)]
pub fn is_adc_irq(&self) -> bool {
*self == Src::AdcIrq
}
#[doc = "AUX_EVCTL:EVSTAT1.MCU_EV"]
#[inline(always)]
pub fn is_mcu_ev(&self) -> bool {
*self == Src::McuEv
}
#[doc = "AUX_EVCTL:EVSTAT1.ACLK_REF"]
#[inline(always)]
pub fn is_aclk_ref(&self) -> bool {
*self == Src::AclkRef
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO15"]
#[inline(always)]
pub fn is_auxio15(&self) -> bool {
*self == Src::Auxio15
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO14"]
#[inline(always)]
pub fn is_auxio14(&self) -> bool {
*self == Src::Auxio14
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO13"]
#[inline(always)]
pub fn is_auxio13(&self) -> bool {
*self == Src::Auxio13
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO12"]
#[inline(always)]
pub fn is_auxio12(&self) -> bool {
*self == Src::Auxio12
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO11"]
#[inline(always)]
pub fn is_auxio11(&self) -> bool {
*self == Src::Auxio11
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO10"]
#[inline(always)]
pub fn is_auxio10(&self) -> bool {
*self == Src::Auxio10
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO9"]
#[inline(always)]
pub fn is_auxio9(&self) -> bool {
*self == Src::Auxio9
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO8"]
#[inline(always)]
pub fn is_auxio8(&self) -> bool {
*self == Src::Auxio8
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO7"]
#[inline(always)]
pub fn is_auxio7(&self) -> bool {
*self == Src::Auxio7
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO6"]
#[inline(always)]
pub fn is_auxio6(&self) -> bool {
*self == Src::Auxio6
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO5"]
#[inline(always)]
pub fn is_auxio5(&self) -> bool {
*self == Src::Auxio5
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO4"]
#[inline(always)]
pub fn is_auxio4(&self) -> bool {
*self == Src::Auxio4
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO3"]
#[inline(always)]
pub fn is_auxio3(&self) -> bool {
*self == Src::Auxio3
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO2"]
#[inline(always)]
pub fn is_auxio2(&self) -> bool {
*self == Src::Auxio2
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO1"]
#[inline(always)]
pub fn is_auxio1(&self) -> bool {
*self == Src::Auxio1
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO0"]
#[inline(always)]
pub fn is_auxio0(&self) -> bool {
*self == Src::Auxio0
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_PROG_WU"]
#[inline(always)]
pub fn is_aon_prog_wu(&self) -> bool {
*self == Src::AonProgWu
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_SW"]
#[inline(always)]
pub fn is_aon_sw(&self) -> bool {
*self == Src::AonSw
}
#[doc = "AUX_EVCTL:EVSTAT0.OBSMUX1"]
#[inline(always)]
pub fn is_obsmux1(&self) -> bool {
*self == Src::Obsmux1
}
#[doc = "AUX_EVCTL:EVSTAT0.OBSMUX0"]
#[inline(always)]
pub fn is_obsmux0(&self) -> bool {
*self == Src::Obsmux0
}
#[doc = "AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL"]
#[inline(always)]
pub fn is_adc_fifo_almost_full(&self) -> bool {
*self == Src::AdcFifoAlmostFull
}
#[doc = "AUX_EVCTL:EVSTAT0.ADC_DONE"]
#[inline(always)]
pub fn is_adc_done(&self) -> bool {
*self == Src::AdcDone
}
#[doc = "AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE"]
#[inline(always)]
pub fn is_smph_autotake_done(&self) -> bool {
*self == Src::SmphAutotakeDone
}
#[doc = "AUX_EVCTL:EVSTAT0.TIMER1_EV"]
#[inline(always)]
pub fn is_timer1_ev(&self) -> bool {
*self == Src::Timer1Ev
}
#[doc = "AUX_EVCTL:EVSTAT0.TIMER0_EV"]
#[inline(always)]
pub fn is_timer0_ev(&self) -> bool {
*self == Src::Timer0Ev
}
#[doc = "AUX_ANAIF:ISRCCTL.RESET_N"]
#[inline(always)]
pub fn is_isrc_reset(&self) -> bool {
*self == Src::IsrcReset
}
#[doc = "AUX_EVCTL:EVSTAT0.AUX_COMPB"]
#[inline(always)]
pub fn is_aux_compb(&self) -> bool {
*self == Src::AuxCompb
}
#[doc = "AUX_EVCTL:EVSTAT0.AUX_COMPA"]
#[inline(always)]
pub fn is_aux_compa(&self) -> bool {
*self == Src::AuxCompa
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_RTC_CH2"]
#[inline(always)]
pub fn is_aon_rtc_ch2(&self) -> bool {
*self == Src::AonRtcCh2
}
}
#[doc = "Field `SRC` writer - 4:0\\]
Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0."]
pub type SrcW<'a, REG> = crate::FieldWriter<'a, REG, 5, Src, crate::Safe>;
impl<'a, REG> SrcW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "AUX_EVCTL:EVSTAT1.ADC_IRQ"]
#[inline(always)]
pub fn adc_irq(self) -> &'a mut crate::W<REG> {
self.variant(Src::AdcIrq)
}
#[doc = "AUX_EVCTL:EVSTAT1.MCU_EV"]
#[inline(always)]
pub fn mcu_ev(self) -> &'a mut crate::W<REG> {
self.variant(Src::McuEv)
}
#[doc = "AUX_EVCTL:EVSTAT1.ACLK_REF"]
#[inline(always)]
pub fn aclk_ref(self) -> &'a mut crate::W<REG> {
self.variant(Src::AclkRef)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO15"]
#[inline(always)]
pub fn auxio15(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio15)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO14"]
#[inline(always)]
pub fn auxio14(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio14)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO13"]
#[inline(always)]
pub fn auxio13(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio13)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO12"]
#[inline(always)]
pub fn auxio12(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio12)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO11"]
#[inline(always)]
pub fn auxio11(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio11)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO10"]
#[inline(always)]
pub fn auxio10(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio10)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO9"]
#[inline(always)]
pub fn auxio9(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio9)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO8"]
#[inline(always)]
pub fn auxio8(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio8)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO7"]
#[inline(always)]
pub fn auxio7(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio7)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO6"]
#[inline(always)]
pub fn auxio6(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio6)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO5"]
#[inline(always)]
pub fn auxio5(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio5)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO4"]
#[inline(always)]
pub fn auxio4(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio4)
}
#[doc = "AUX_EVCTL:EVSTAT1.AUXIO3"]
#[inline(always)]
pub fn auxio3(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio3)
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO2"]
#[inline(always)]
pub fn auxio2(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio2)
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO1"]
#[inline(always)]
pub fn auxio1(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio1)
}
#[doc = "AUX_EVCTL:EVSTAT0.AUXIO0"]
#[inline(always)]
pub fn auxio0(self) -> &'a mut crate::W<REG> {
self.variant(Src::Auxio0)
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_PROG_WU"]
#[inline(always)]
pub fn aon_prog_wu(self) -> &'a mut crate::W<REG> {
self.variant(Src::AonProgWu)
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_SW"]
#[inline(always)]
pub fn aon_sw(self) -> &'a mut crate::W<REG> {
self.variant(Src::AonSw)
}
#[doc = "AUX_EVCTL:EVSTAT0.OBSMUX1"]
#[inline(always)]
pub fn obsmux1(self) -> &'a mut crate::W<REG> {
self.variant(Src::Obsmux1)
}
#[doc = "AUX_EVCTL:EVSTAT0.OBSMUX0"]
#[inline(always)]
pub fn obsmux0(self) -> &'a mut crate::W<REG> {
self.variant(Src::Obsmux0)
}
#[doc = "AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL"]
#[inline(always)]
pub fn adc_fifo_almost_full(self) -> &'a mut crate::W<REG> {
self.variant(Src::AdcFifoAlmostFull)
}
#[doc = "AUX_EVCTL:EVSTAT0.ADC_DONE"]
#[inline(always)]
pub fn adc_done(self) -> &'a mut crate::W<REG> {
self.variant(Src::AdcDone)
}
#[doc = "AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE"]
#[inline(always)]
pub fn smph_autotake_done(self) -> &'a mut crate::W<REG> {
self.variant(Src::SmphAutotakeDone)
}
#[doc = "AUX_EVCTL:EVSTAT0.TIMER1_EV"]
#[inline(always)]
pub fn timer1_ev(self) -> &'a mut crate::W<REG> {
self.variant(Src::Timer1Ev)
}
#[doc = "AUX_EVCTL:EVSTAT0.TIMER0_EV"]
#[inline(always)]
pub fn timer0_ev(self) -> &'a mut crate::W<REG> {
self.variant(Src::Timer0Ev)
}
#[doc = "AUX_ANAIF:ISRCCTL.RESET_N"]
#[inline(always)]
pub fn isrc_reset(self) -> &'a mut crate::W<REG> {
self.variant(Src::IsrcReset)
}
#[doc = "AUX_EVCTL:EVSTAT0.AUX_COMPB"]
#[inline(always)]
pub fn aux_compb(self) -> &'a mut crate::W<REG> {
self.variant(Src::AuxCompb)
}
#[doc = "AUX_EVCTL:EVSTAT0.AUX_COMPA"]
#[inline(always)]
pub fn aux_compa(self) -> &'a mut crate::W<REG> {
self.variant(Src::AuxCompa)
}
#[doc = "AUX_EVCTL:EVSTAT0.AON_RTC_CH2"]
#[inline(always)]
pub fn aon_rtc_ch2(self) -> &'a mut crate::W<REG> {
self.variant(Src::AonRtcCh2)
}
}
#[doc = "Field `RESERVED5` reader - 5:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
pub type Reserved5R = crate::BitReader;
#[doc = "Field `RESERVED5` writer - 5:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
pub type Reserved5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "6:6\\]
Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ratio {
#[doc = "1: Prescaler divides input by 64. AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input."]
Div64 = 1,
#[doc = "0: Prescaler divides input by 16. AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input."]
Div16 = 0,
}
impl From<Ratio> for bool {
#[inline(always)]
fn from(variant: Ratio) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RATIO` reader - 6:6\\]
Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler."]
pub type RatioR = crate::BitReader<Ratio>;
impl RatioR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ratio {
match self.bits {
true => Ratio::Div64,
false => Ratio::Div16,
}
}
#[doc = "Prescaler divides input by 64. AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input."]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == Ratio::Div64
}
#[doc = "Prescaler divides input by 16. AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input."]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == Ratio::Div16
}
}
#[doc = "Field `RATIO` writer - 6:6\\]
Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler."]
pub type RatioW<'a, REG> = crate::BitWriter<'a, REG, Ratio>;
impl<'a, REG> RatioW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Prescaler divides input by 64. AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input."]
#[inline(always)]
pub fn div64(self) -> &'a mut crate::W<REG> {
self.variant(Ratio::Div64)
}
#[doc = "Prescaler divides input by 16. AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input."]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(Ratio::Div16)
}
}
#[doc = "Field `RESET_N` reader - 7:7\\]
Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler."]
pub type ResetNR = crate::BitReader;
#[doc = "Field `RESET_N` writer - 7:7\\]
Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler."]
pub type ResetNW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESERVED8` reader - 31:8\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
pub type Reserved8R = crate::FieldReader<u32>;
#[doc = "Field `RESERVED8` writer - 31:8\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
pub type Reserved8W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:4 - 4:0\\]
Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0."]
#[inline(always)]
pub fn src(&self) -> SrcR {
SrcR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 5 - 5:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved5(&self) -> Reserved5R {
Reserved5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler."]
#[inline(always)]
pub fn ratio(&self) -> RatioR {
RatioR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler."]
#[inline(always)]
pub fn reset_n(&self) -> ResetNR {
ResetNR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31 - 31:8\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved8(&self) -> Reserved8R {
Reserved8R::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - 4:0\\]
Prescaler event source. Select an event from the asynchronous AUX event bus to connect to the prescaler input. Configure only while RESET_N is 0."]
#[inline(always)]
#[must_use]
pub fn src(&mut self) -> SrcW<PrectlSpec> {
SrcW::new(self, 0)
}
#[doc = "Bit 5 - 5:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
#[must_use]
pub fn reserved5(&mut self) -> Reserved5W<PrectlSpec> {
Reserved5W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Prescaler ratio. This controls how often the AUX_TDC_PRE event is generated by the prescaler."]
#[inline(always)]
#[must_use]
pub fn ratio(&mut self) -> RatioW<PrectlSpec> {
RatioW::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Prescaler reset. 0: Reset prescaler. 1: Release reset of prescaler. AUX_TDC_PRE event becomes 0 when you reset the prescaler."]
#[inline(always)]
#[must_use]
pub fn reset_n(&mut self) -> ResetNW<PrectlSpec> {
ResetNW::new(self, 7)
}
#[doc = "Bits 8:31 - 31:8\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
#[must_use]
pub fn reserved8(&mut self) -> Reserved8W<PrectlSpec> {
Reserved8W::new(self, 8)
}
}
#[doc = "Prescaler Control The prescaler can be used to count events that are faster than the AUX clock frequency. It can be used to: - count pulses on a specified event from the asynchronous event bus. - prescale a specified event from the asynchronous event bus. To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE. It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX clock frequency.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prectl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prectl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrectlSpec;
impl crate::RegisterSpec for PrectlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prectl::R`](R) reader structure"]
impl crate::Readable for PrectlSpec {}
#[doc = "`write(|w| ..)` method takes [`prectl::W`](W) writer structure"]
impl crate::Writable for PrectlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PRECTL to value 0x1f"]
impl crate::Resettable for PrectlSpec {
const RESET_VALUE: u32 = 0x1f;
}