calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r = std_reg(32);
    exp0 = exponent();
  }
  wires {
    group upd0<"promotable"=1> {
      r.in = 32'd1;
      r.write_en = 1'd1;
      upd0[done] = r.done;
    }
  }
  control {
    @promotable(3) seq {
      @promotable upd0;
      @promotable(2) invoke exp0(
        base = r.out,
        exp = r.out
      )();
    }
  }
}
component exponent(base: 32, exp: 32, @go @promotable(2) go: 1, @clk clk: 1, @reset reset: 1) -> (out: 32, @done done: 1) {
  cells {
    r1 = std_reg(32);
    r2 = std_reg(32);
  }
  wires {
    group upd2<"promotable"=1> {
      r2.in = 32'd1;
      r2.write_en = 1'd1;
      upd2[done] = r2.done;
    }
    group upd1<"promotable"=1> {
      r1.in = 32'd1;
      r1.write_en = 1'd1;
      upd1[done] = r1.done;
    }
  }
  control {
    @promotable(2) seq {
      @promotable upd1;
      @promotable upd2;
    }
  }
}