calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    a = std_reg(2);
    b = std_reg(2);
    c = std_reg(2);
  }
  wires {
    group A<"promotable"=1> {
      a.in = 2'd0;
      a.write_en = 1'd1;
      A[done] = a.done;
    }
    group B<"promotable"=1> {
      b.in = 2'd1;
      b.write_en = 1'd1;
      B[done] = b.done;
    }
    group C<"promotable"=1> {
      c.in = 2'd2;
      c.write_en = 1'd1;
      C[done] = c.done;
    }
  }
  control {
    @promotable(3) seq {
      @promotable A;
      @promotable B;
      @promotable C;
    }
  }
}