calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

import "primitives/core.futil";
import "primitives/memories/comb.futil";
static<2> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    add = std_add(32);
    r = std_reg(32);
    @generated fsm = std_reg(2);
    @generated adder = std_add(2);
  }
  wires {
    static<1> group a {
      r.write_en = 1'd1;
      add.right = right;
      add.left = left;
      r.in = add.out;
    }
    static<1> group b {
      r.write_en = 1'd1;
      add.right = right;
      add.left = r.out;
      r.in = add.out;
    }
    static<2> group static_seq {
    }
    r.write_en = go & fsm.out == 2'd0 ? 1'd1;
    add.right = go & fsm.out == 2'd0 ? right;
    add.left = go & fsm.out == 2'd0 ? left;
    r.in = go & fsm.out == 2'd0 ? add.out;
    r.write_en = fsm.out == 2'd1 ? 1'd1;
    add.right = fsm.out == 2'd1 ? right;
    add.left = fsm.out == 2'd1 ? r.out;
    r.in = fsm.out == 2'd1 ? add.out;
    adder.left = fsm.out;
    adder.right = 2'd1;
    fsm.write_en = 1'd1;
    fsm.in = go & fsm.out == 2'd0 ? 2'd1;
    fsm.in = fsm.out != 2'd0 & fsm.out != 2'd1 ? adder.out;
    fsm.in = fsm.out == 2'd1 ? 2'd0;
  }
  control {}
}
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    a = do_add();
  }
  wires {
    static<2> group static_invoke {
      a.go = %0 ? 1'd1;
      a.left = 32'd5;
      a.right = 32'd6;
    }
  }
  control {
    static_invoke;
  }
}