calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    add = std_add(32);
    r = std_reg(32);
    @generated fsm = std_reg(3);
    @generated adder = std_add(3);
  }
  wires {
    static<1> group a {
      r.write_en = 1'd1;
      add.right = right;
      add.left = r.out;
      r.in = add.out;
    }
    static<1> group b {
      r.write_en = 1'd1;
      add.right = right;
      add.left = left;
      r.in = add.out;
    }
    static<6> group static_seq {
    }
    static<5> group static_repeat {
      a[go] = 1'd1;
    }
    r.write_en = go & fsm.out == 3'd0 ? 1'd1;
    add.right = go & fsm.out == 3'd0 ? right;
    add.left = go & fsm.out == 3'd0 ? left;
    r.in = go & fsm.out == 3'd0 ? add.out;
    a[go] = fsm.out >= 3'd1 & fsm.out < 3'd6 ? 1'd1;
    adder.left = fsm.out;
    adder.right = 3'd1;
    fsm.write_en = 1'd1;
    fsm.in = go & fsm.out == 3'd0 ? 3'd1;
    fsm.in = fsm.out != 3'd0 & fsm.out != 3'd5 ? adder.out;
    fsm.in = fsm.out == 3'd5 ? 3'd0;
  }
  control {}
}
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    a = do_add();
  }
  wires {
    static<6> group static_invoke {
      a.go = %0 ? 1'd1;
      a.left = 32'd5;
      a.right = 32'd6;
    }
  }
  control {
    static_invoke;
  }
}