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// -p compile-repeat
import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main() -> () {
cells {
r1 = std_reg(32);
r2 = std_reg(32);
}
wires {
group write_r1 {
r1.in = 32'd2;
r1.write_en = 1'd1;
write_r1[done] = r1.done;
}
group write_r2 {
r2.in = 32'd2;
r2.write_en = 1'd1;
write_r2[done] = r2.done;
}
}
control {
repeat 4 {
seq {
write_r1;
write_r2;
}
}
repeat 0 {
seq {
write_r1;
write_r2;
}
}
repeat 1 {
seq {
write_r1;
write_r2;
}
}
}
}