calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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// -p compile-repeat
import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main() -> () {
  cells {
    r1 = std_reg(32);
  }
  wires {
    group write_r1 {
      r1.in = 32'd2;
      r1.write_en = 1'd1;
      write_r1[done] = r1.done;
    }
  }
  control {
    repeat 4 {
      repeat 2 {
        write_r1;
      }
    }
  }
}