calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
static<2> component add_one(@go go: 1, @clk clk: 1, @reset reset: 1, out_read_data: 32, out_done: 1) -> (@done done: 1, out_addr0: 1, out_write_data: 32, out_write_en: 1) {
  cells {
    add = std_add(32);
    r = std_reg(32);
  }
  wires {
    static<1> group add_1 {
      add.left = 32'd1;
      add.right = 32'd1;
      r.in = add.out;
      r.write_en = 1'd1;
    }
    static<1> group reg_to_mem {
      out_write_data = r.out;
      out_addr0 = 1'd0;
      out_write_en = 1'd1;
    }
  }
  control {
    static<2> seq  {
      add_1;
      reg_to_mem;
    }
  }
}
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    adder = add_one();
    @external mem = comb_mem_d1(32, 1, 1);
    add = std_add(32);
    r = std_reg(32);
  }
  wires {
    group add_1 {
      add.left = mem.read_data;
      mem.addr0 = 1'd0;
      add.right = 32'd1;
      r.in = add.out;
      r.write_en = 1'd1;
      add_1[done] = r.done;
    }
    group reg_to_mem {
      mem.addr0 = 1'd0;
      mem.write_data = r.out;
      mem.write_en = 1'd1;
      reg_to_mem[done] = mem.done;
    }
    static<2> group static_invoke {
      mem.addr0 = adder.out_addr0;
      mem.write_data = adder.out_write_data;
      mem.write_en = adder.out_write_en;
      adder.out_read_data = mem.read_data;
      adder.out_done = mem.done;
      adder.go = %0 ? 1'd1;
    }
  }
  control {
    seq {
      static_invoke;
      add_1;
      reg_to_mem;
    }
  }
}