calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/compile.futil";
component foo(@go go: 1, @clk clk: 1, @reset reset: 1, r_out: 32, r_done: 1) -> (@done done: 1, r_in: 32, r_write_en: 1) {
  cells {
  }
  wires {
    group reg_to_mem {
      r_in = 32'd10;
      r_write_en = 1'd1;
      reg_to_mem[done] = r_done;
    }
  }
  control {
    seq {
      if r_out {
        reg_to_mem;
      }
    }
  }
}
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    f = foo();
    r0 = std_reg(32);
  }
  wires {
    group invoke0 {
      r0.in = f.r_in;
      r0.write_en = f.r_write_en;
      f.r_out = r0.out;
      f.r_done = r0.done;
      f.go = 1'd1;
      invoke0[done] = f.done;
    }
  }
  control {
    invoke0;
  }
}