import "primitives/core.futil";
component add(left: 32, right: 32, go: 1, clk: 1, @go go0: 1, @clk clk0: 1, @reset reset: 1) -> (out: 32, done: 1, @done done0: 1) {
cells {
adder = std_add(32);
outpt = std_reg(32);
}
wires {
group do_add {
adder.left = left;
adder.right = right;
outpt.in = adder.out;
outpt.write_en = 1'd1;
do_add[done] = outpt.done;
}
}
control {
seq {
do_add;
}
}
}
component main(go: 1, clk: 1, @go go0: 1, @clk clk0: 1, @reset reset: 1) -> (done: 1, @done done0: 1) {
cells {
x = std_reg(32);
add_x = std_add(32);
my_add = add();
y = std_reg(32);
}
wires {
group wr_x {
x.in = 32'd1;
x.write_en = 1'd1;
wr_x[done] = x.done;
}
group rd_x {
add_x.left = x.out;
add_x.right = x.out;
rd_x[done] = 1'd1;
}
group wr_y {
y.in = 32'd10;
y.write_en = 1'd1;
wr_y[done] = y.done;
}
}
control {
seq {
wr_x;
rd_x;
wr_y;
invoke my_add(
left = y.out,
right = 32'd1
)();
}
}
}