calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main() -> () {
  cells {
    r = std_reg(32);
  }
  wires {
    group one {
      r.in = 32'd0;
      r.write_en = 1'd1;
      one[done] = r.done;
    }
    group two {
      r.in = 32'd2;
      r.write_en = 1'd1;
      two[done] = r.done;
    }
    // need this group so that r is read from, so that it is
    // not removed in the `dead-cell-removal` pass, since we want the error
    // to occur.
    group read_r {
      r.in = r.out;
      r.write_en = 1'd1;
      read_r[done] = r.done;
    }
  }
  control {
    par { one; two; }
    read_r;
  }
}