calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/pipelined.futil";

component main () -> () {
  cells {
    @external p = comb_mem_d1(3,1,1);
    incr = std_add(3);
    l = std_lt(3);
    r = std_reg(1);
    s = std_reg(3);
  }

  wires {
    static<1> group A {
      incr.left = p.read_data;
      incr.right = 3'd1;
      s.in = incr.out;
      s.write_en = %0 ? 1'd1;
      p.addr0 = 1'd0;
    }

    static<1> group C {
      p.write_data = s.out;
      p.write_en = 1'd1;
      p.addr0 = 1'd0;
    }

    static<1> group B {
      l.left = p.read_data;
      l.right = 3'd6;
      r.in = l.out;
      r.write_en = 1'd1;
      p.addr0 = 1'd0;
    }
  }

  control {
    seq {
      B;
      while r.out {
        static seq {A;C; B;}
      }
    }
  }
}